CXB1818Q 데이터 시트보기 (PDF) - Sony Semiconductor

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CXB1818Q

Laser Diode Driver

Sony Semiconductor 

CXB1818Q

Description of Each Function Block

1. Data Buffer, Clock Buffer

Data Buffer and Clock Buffer are comprised of the data buffer, clock buffer, DFF, MUX and delay generator.

ECL/PECL data is input to the data buffer at a maximum data rate of 622Mbps. The input data DFF selection

pin (Pin 19 FFSel) can select whether the input data is used in through mode or the signal which is corrected

by the clock signal in the DFF is used. When the FFSel is open, the data becomes through mode, when the

FFsel is connected VEE,the data becomes DFF mode.

And, this data is input to the delay circuit. The delay circuit adds a delay to the falling edge of the pulse up to a

maximum of 1.0ns for the D input signal High pulse (Q output current pulse). The delay is set by an external

resistor between the delay set pin (Pin 31 Tset) and VCC. The relation between the High pulse width and the

set resistance (Rset) is shown in Fig. 1.

The Vbb generator provides a reference bias current to the data buffer for AC coupling inputs.

2. Modulation Current Generator

This circuit modulates the laser diode and the modulation current can be set by feeding the current to the

modulation current set pin (Pin 14 DrvAdj). The relation between the modulation current (IQ) and the modulation

set current (IQset) is shown in Fig. 2. There is also a modulation current monitor pin (Pin 13 DrvMon) that

allows the IC user to monitor the modulation current by putting an external fixed resistor between VCC and

DrvMon pins, and the modulation current can be monitored by measuring the voltage of DrvMon pin. The

relation between the modulation current (IQ) and the DrvMon current (Idrvmon) is shown in Fig. 7.

3. Laser Diode Bias Current Generator

This circuit is a very large current source capable of sourcing up to 60mA of bias current to the laser diode.

The circuit is a 22 to 1 (for current – current setting) current mirror that can be controlled externally two ways.

The first method is to short BiasAdj (Pin 3) and SBias (Pin 4) together and inject a control current (IBset) into

the two pins. Bias (Pin 5) is connected to the laser diode. Laser diode bias current vs. control current (IBset)

characteristics is shown in Fig. 3.

The second method is to tie SBias (Pin 4) to VCC and tune BiasAdj (Pin 3) with a voltage source. Varying the

voltage at the BiasAdj pin will vary the current through the laser diode. Laser diode bias current vs. control

voltage characteristics is shown in Fig. 4.

4. APC (Automatic Power Control) Circuit

The APC circuit is comprised of the window comparator, APC OpAmp, and laser diode alarm circuit.

The APC OpAmp is normally configured as an inverting integrator. The inverting input is connected to the

photodiode that monitors the optical power output from the laser diode. The photodiode converts the optical

power received from the laser diode to a current. The output of the OpAmp then drives the laser diode current

bias adjust pin (BiasAdj), and the laser diode current bias set pin (SBias) is shorted to VCC via a resistor. With

the OpAmp configured as an inverting integrator, the OpAmp can tune the laser diode current inversely to the

current in the photodiode. That is to say that if a Low current is detected by the photodiode the integrator

output goes up causing more bias current to flow through the laser diode. If the photodiode current is High, the

output of the OpAmp will go Low causing less bias current to flow through the laser diode.

When the output of the APC OpAmp (Pin 40 APCOut) is connected to the window comparator input pin (Pin 38

WCompIn), the function of the window comparator detects the voltage which is outside of the reference voltage

range for each comparator (RS, RSB). When this happens, the comparator outputs cause the laser diode

alarm output (LDAlm) to go High alerting the system that the laser diode current is in the outside of the range.

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