AD9731(RevA) 데이터 시트보기 (PDF) - Analog Devices
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AD9731 Datasheet PDF : 11 Pages
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5/27/99 8 PM
AD9731–SPECIFICATIONS (+VS = +5 V, –VS = –5.2 V, CLOCK = 125 MHz, RSET = 1.96 k⍀ for 20.4 mA IOUT,
VREF = –1.25 V, unless otherwise noted.)
Parameter
Temp
Test Level
Min
Typ
Max
Units
RESOLUTION
10
Bits
THROUGHPUT RATE
+25°C
IV
165
170
MHz
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
+25°C
I
Full
VI
+25°C
I
Full
VI
0.25
1
LSB
0.35
1.5
LSB
0.6
1
LSB
0.7
1.5
LSB
INITIAL OFFSET ERROR
Zero-Scale Offset Error
Full-Scale Gain Error1
Offset Drift Coefficient
+25°C
I
Full
VI
+25°C
I
Full
VI
V
35
70
40
100
2.5
5
2.5
5
0.04
µA
µA
% FS
% FS
µA/°C
REFERENCE/CONTROL AMP
Internal Reference Voltage2
Internal Reference Voltage Drift
Internal Reference Output Current3
Amplifier Input Impedance
Amplifier Bandwidth
REFERENCE INPUT4
Reference Input Impedance
Reference Multiplying Bandwidth5
+25°C
I
Full
IV
Full
VI
+25°C
V
+25°C
V
+25°C
V
+25°C
V
–1.35
–50
–1.25
100
50
2.5
4.6
75
–1.15
+500
V
µV/°C
µA
kΩ
MHz
kΩ
MHz
OUTPUT PERFORMANCE
Output Current4, 6
Output Compliance
Output Resistance
Output Capacitance
Voltage Settling Time to 1/2 LSB (tST)7
Propagation Delay (tPD)8
Glitch Impulse9
Output Slew Rate10
Output Rise Time10
Output Fall Time10
+25°C
V
+25°C
IV
+25°C
V
+25°C
V
+25°C
V
+25°C
V
+25°C
V
+25°C
V
+25°C
V
+25°C
V
20
mA
–1.5
+3
V
240
Ω
5
pF
3.8
ns
2.9
ns
4.1
pVs
400
V/µs
1
ns
1
ns
DIGITAL INPUTS
Input Capacitance
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Minimum Data Setup Time (tS)11
Minimum Data Hold Time (tH)12
Clock Pulsewidth Low (pwMIN)
Clock Pulsewidth High (pwMAX)
SFDR PERFORMANCE (Wideband) 13
2 MHz AOUT
10 MHz AOUT
20 MHz AOUT
40 MHz AOUT
65 MHz AOUT (Clock = 170 MHz)
70 MHz AOUT (Clock = 170 MHz)
Full
IV
Full
VI
Full
VI
+25°C
VI
+25°C
VI
+25°C
IV
Full
IV
+25°C
IV
Full
IV
+25°C
IV
+25°C
IV
+25°C
V
+25°C
V
+25°C
V
+25°C
V
+25°C
V
+25°C
V
2
pF
2.0
V
0.8
V
8
50
µA
30
100
µA
1.2
2
ns
1.5
2.5
ns
0.1
1.0
ns
0.1
1.0
ns
2
ns
2
ns
66
dB
62
dB
61
dB
55
dB
50
dB
47
dB
–2–
REV. A
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