74HC160(2019) 데이터 시트보기 (PDF) - NXP Semiconductors.
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74HC160 Datasheet PDF : 15 Pages
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Nexperia
74HC160
Presettable synchronous BCD decade counter; asynchronous reset
10.1. Waveforms and test circuit
VI
CP input
1/fmax
VM
GND
tW
tPHL
tPLH
Fig. 8.
VOH
Qn, TC
output
VOL
90 %
VM
10 %
tTHL
10 %
90 %
tTLH
aaa-012353
Measurement points are given in Table 8.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
The clock (CP) to outputs (Qn, TC) propagation delays, pulse width, output transition times and maximum
frequency
Fig. 9.
VI
CET input
VM
GND
VOH
tPLH
90 %
tPHL
90 %
TC output
VOL
10 %
VM
tTLH
10 %
tTHL
aaa-012354
Measurement points are given in Table 8.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
The count enable carry input (CET) to terminal count output (TC) propagation delays and output transition
times
VI
MR input
VM
GND
VI
trec
tW
CP input
GND
VOH
VM
tPHL
Qn, TC output
VM
VOL
mna913
Measurement points are given in Table 8.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 10. The master reset (MR) pulse width, master reset to output (Qn, TC) propagation delays, and the master
reset to clock (CP) recovery times
74HC160
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 27 March 2019
© Nexperia B.V. 2019. All rights reserved
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