MKP383515040JKM2T0 데이터 시트보기 (PDF) - Vishay Semiconductors
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MKP383515040JKM2T0
Vishay Semiconductors
MKP383515040JKM2T0 Datasheet PDF : 16 Pages
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www.vishay.com
MKP383
Vishay BCcomponents
APPLICATION NOTE AND LIMITING CONDITIONS
For capacitors connected in parallel, normally the proof voltage and possibly the rated voltage must be reduced. For information
depending of the capacitance value and the number of parallel connections contact: dc-film@vishay.com
These capacitors are not suitable for mains applications as across-the-line capacitors without additional protection, as
described hereunder. These mains applications are strictly regulated in safety standards and therefore electromagnetic
interference suppression capacitors conforming the standards must be used.
To select the capacitor for a certain application, the following conditions must be checked:
1. The peak voltage (Up) shall not be greater than the rated DC voltage (URDC)
2. The peak-to-peak voltage (Up-p) shall not be greater than the maximum (Up-p) to avoid the ionization inception level
3. The voltage pulse slope (dU/dt) shall not exceed the rated voltage pulse slope in an RC-circuit at rated voltage and without
ringing. If the pulse voltage is lower than the rated DC voltage, the rated voltage pulse slope may be multiplied by URDC and
divided by the applied voltage.
For all other pulses following equation must be fulfilled:
2
T
x
d--d--U-t--
2
0
x
dt
<
URDC
x
d--d--U-t--
rated
T is the pulse duration
4. The maximum component surface temperature rise must be lower than the limits (see graph max. allowed component
temperature rise).
5. Since in circuits used at voltages over 280 V peak-to-peak the risk for an intrinsically active flammability after a capacitor
breakdown (short circuit) increases, it is recommended that the power to the component is limited to 100 times the values
mentioned in the table: “Heat Conductivity”
6. When using these capacitors as across-the-line capacitor in the input filter for mains applications or as series connected
with an impedance to the mains the applicant must guarantee that the following conditions are fulfilled in any case (spikes
and surge voltages from the mains included).
VOLTAGE CONDITIONS FOR 6 ABOVE
ALLOWED VOLTAGES
Maximum continuous RMS voltage
Maximum temperature RMS-over voltage (< 24 h)
Maximum peak voltage (Vo-p) (< 2 s)
Tamb ≤ 85 °C
URAC
1.25 x URAC
1.6 x URDC
85 °C < Tamb ≤ 105 °C
URAC
1.25 x URAC
1.1 x URDC
EXAMPLE
C = 4n7 - 1600 V used for the voltage signal shown in next drawing.
Up-p = 1000 V; Up = 900 V; T1 = 12 μs; T2 = 64 μs; T3 = 4 μs
The ambient temperature is 80 °C. In case of failure, the oscillation is blocked.
Checking conditions:
1. The peak voltage Up = 900 V is lower than 1600 VDC
2. The peak-to-peak voltage 1000 V is lower than 22 x 550 VAC = 1600 Up-p
3. The voltage pulse slope (dU/dt) = 1000 V/4 μs = 250 V/μs. This is lower than 8000 V/μs (see specific reference data for each
version).
4. The dissipated power is 35 mW as calculated with fourier terms and typical tgd.
The temperature rise for wmax. = 6.0 mm and pitch = 15 mm will be 35 mW / 11 mW/°C = 3.2 °C
This is lower than 10 °C temperature rise at 80 °C, according graph.
5. Oscillation is blocked
6. Not applicable
Revision: 08-Aug-2018
11
Document Number: 28173
For technical questions, contact: dc-film@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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