SCC2681 데이터 시트보기 (PDF) - NXP Semiconductors.
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SCC2681 Datasheet PDF : 29 Pages
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Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product data
SCC2681
AC CHARACTERISTICS
Tamb = –40 °C to +85 °C1; VCC = +5.0 V ± 10% 2, 3, 4, 5
SYMBOL
PARAMETER
LIMITS
Min
Typ
Max
UNIT
Reset Timing (Figure 3)
tRES
RESET pulse width
Bus Timing (Figure 4)6
200
–
–
ns
tAS
A0-A3 set-up time to RDN, WRN LOW
tAH
A0-A3 hold time from RDN, WRN LOW
tCS
CEN set-up time to RDN, WRN LOW
tCH
CEN hold time from RDN, WRN HIGH
tRW
WRN, RDN pulse width
tDD
Data valid after RDN LOW
tDF
Data bus floating after RDN HIGH
tDS
Data set-up time before WRN HIGH
tDH
tRWD
Data hold time after WRN HIGH
HIGH time between READs and/or WRITE7, 8
Port Timing (Figure 5)6
10
–
–
ns
100
–
–
ns
0
–
–
ns
0
–
–
ns
225
–
–
ns
–
–
175
ns
–
–
100
ns
100
–
–
ns
20
–
–
ns
200
–
–
ns
tPS
Port input set-up time before RDN LOW
tPH
Port input hold time after RDN HIGH
tPD
Port output valid after WRN HIGH
Interrupt Timing (Figure 6)
0
–
–
ns
0
–
–
ns
–
–
400
ns
tIR
INTRN (or OP3-OP7 when used as interrupts) negated from:
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
Reset command (delta break interrupt)
Stop C/T command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
–
–
300
ns
–
–
300
ns
–
–
300
ns
–
–
300
ns
–
–
300
ns
–
–
300
ns
Clock Timing (Figure 7)10
tCLK
fCLK
tCTC
fCTC
tRX9
fRX9
tTX9
fTX9
X1/CLK HIGH or LOW time
X1/CLK frequency
CTCLK (IP2) HIGH or LOW time
CTCLK (IP2) frequency
RxC HIGH or LOW time
RxC frequency (16×)
(1×)
TxC HIGH or LOW time
TxC frequency (16×)
(1×)
100
–
–
1.0
3.6864
4.0
100
–
–
0
–
4.0
220
–
–
0
–
2.0
0
–
1.0
220
–
–
0
–
2.0
0
–
1.0
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
Transmitter Timing (Figure 8)
tTXD9
tTCS9
TxD output delay from TxC external clock input on IP pin
Output delay from TxC LOW at OP pin to TxD data output
Receiver Timing (Figure 10)
–
–
350
ns
0
–
150
ns
tRXS9
tRXH9
RxD data setup time before RxC HIGH at external clock input on IP pin
RxD data hold time after RxC HIGH at external clock input on IP pin
240
–
–
ns
200
–
–
ns
NOTES:
1. For operating at elevated temperatures, the device must be derated based on +150 °C maximum junction temperature.
2. Parameters are valid over specified temperature range.
3. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4 V and 2.4 V with a
transition time of ≤ 20 ns. For X1/CLK this swing is between 0.4 V and 4.4 V. All time measurements are referenced at input voltages of
0.8 V and 2.0 V as appropriate.
4. Typical values are at +25 °C, typical supply voltages, and typical processing parameters.
5. Test condition for outputs: CL = 150 pF, except interrupt outputs. Test condition for interrupt outputs: CL = 50 pF, RL = 2.7 kΩ to VCC.
6. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. In this
case, all timing specifications apply referenced to the falling and rising edges of CEN, CEN and RDN (also CEN and WRN) are ANDed
internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle.
7. If CEN is used as the ‘strobing’ input, the parameter defines the minimum HIGH times between one CEN and the next. The RDN signal must
be negated for tRWD to guarantee that any status register changes are valid.
2004 Apr 06
6
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