A3G4250D 데이터 시트보기 (PDF) - STMicroelectronics
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A3G4250D Datasheet PDF : 44 Pages
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A3G4250D
7
Register description
Register description
7.1
7.2
The device contains a set of registers which are used to control its behavior and to retrieve
rate data. The register addresses, made up of 7 bits, are used to identify them and to write
the data through the serial interface.
WHO_AM_I (0Fh)
Table 19. WHO_AM_I register
1
1
0
1
0
0
1
1
Device identification register.
CTRL_REG1 (20h)
Table 20. CTRL_REG1 register
DR1
DR0
BW1
BW0
PD
Zen
Yen
Xen
Table 21. CTRL_REG1 description
DR1-DR0 Output data rate selection. Refer to Table 22
BW1-BW0 Bandwidth selection. Refer to Table 22
Power-down mode enable. Default value: 0
PD
(0: power-down mode, 1: normal mode or sleep mode)
Zen
Z-axis enable. Default value: 1
(0: Z-axis disabled; 1: Z-axis enabled)
Yen
Y-axis enable. Default value: 1
(0: Y-axis disabled; 1: Y-axis enabled)
Xen
X-axis enable. Default value: 1
(0: X-axis disabled; 1: X-axis enabled)
DR<1:0> is used to set ODR selection. BW <1:0> is used to set Bandwidth selection.
In the following table (Table 22) all frequencies resulting in a combination of DR / BW bits
are reported.
Table 22. DR and BW configuration setting
DR <1:0>
BW <1:0>
ODR [Hz]
00
00
100
00
01
100
00
10
100
00
11
100
Cut-off
12.5
25
25
25
Doc 022768 Rev 3
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