MSM9405MB 데이터 시트보기 (PDF) - Oki Electric Industry

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MSM9405MB

IrDA Communication Controller

Oki Electric Industry 

¡ Semiconductor

MSM9405

• LSR: Line Status Register (Read Only) (Address = 3h)

The LSR (Line Status Register) indicates various statuses of the MSM9405 that is running. When

the system is reset, all bits of the LSR are set to "0". This register is for read only and cannot be

written.

LSR LSR LSR LSR LSR LSR LSR LSR

7

6

5

4

3

2

1

0

TOUT (Timeout = "1")

IR_DET (SIR Pulse detect = "1")

FLV (Byte number in FIFO)

LSR bit

LSR[0]

LSR[1]

LSR[2-7]

Description

TOUT (FIFO Timeout): When time-out occurs in the FIFO during receiving, this bit is set to "1".

When received data is read from the FIFO, TOUT is set to "0".

IR_DET (SIR Pulse detect) : This bit is set to "1" when a pulse having a width of tspw (SIR pulse width

upon receiving). It is set to "0" when the CPU reads the LSR.

FLV (FIFO Level): These bits indicate the number of data items in the FIFO with a value of 0 to 32.

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