![](/html/ON-Semiconductor/849392/page6.png)
CAT24AA04, CAT24AA08
BUS ACTIVITY:
MASTER
S
T
A
R
SLAVE
ADDRESS
T
a9 a8
S
*
ADDRESS
BYTE
a7 ÷ a0
DATA
BYTE
S
T
O
d7 ÷ d0
P
P
SLAVE
A
A
A
C
C
C
K
K
K
*a9 = 0 for CAT24AA04
Figure 6. Byte Write Sequence
SCL
SDA
8th Bit
Byte n
ACK
tWR
STOP
CONDITION
Figure 7. Write Cycle Timing
START
CONDITION
ADDRESS
BUS ACTIVITY: S
T
A
MASTER R
T
S
SLAVE
ADDRESS
a9 a8
*
ADDRESS
BYTE
a7 ÷ a0
DATA
BYTE
n
d7 ÷ d0
DATA
BYTE
n+1
SLAVE
A
A
A
A
C
C
C
C
K
K
K
K
n=1
x ≤ 15
*a9 = 0 for CAT24AA04
Figure 8. Page Write Sequence
DATA
S
BYTE T
n+x
O
P
P
A
C
K
ADDRESS
BYTE
DATA
BYTE
1
8
9
1
8
SCL
SDA
a7
a0
d7
d0
tSU:WP
WP
tHD:WP
Figure 9. WP Timing
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