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23LC512T-E

512Kbit SPI Serial SRAM with SDI and SQI Interface

Microchip Technology 

23A512/23LC512

2.5 Read Mode Register Instruction

(RDMR)

The Read Mode Register instruction (RDMR) provides

access to the MODE register. The MODE register may

be read at any time. The MODE register is formatted as

follows:

TABLE 2-2: MODE REGISTER

7

6

54321 0

W/R W/R – – – – – –

MODE MODE 0 0 0 0 0 0

W/R = writable/readable

The mode bits indicate the operating mode of the

SRAM. The possible modes of operation are:

0 0 = Byte mode

1 0 = Page mode

0 1 = Sequential mode (default operation)

1 1 = Reserved

Bits 0 through 5 are reserved and should always be set

to ‘0’.

See Figure 2-7 for the RDMR timing sequence.

FIGURE 2-7: READ MODE REGISTER TIMING SEQUENCE (RDMR)

CS

SCK

SI

SO

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction

0 00 00 1 01

High-Impedance

Data from MODE Register

7 6 54 3 2 10

DS20005155B-page 10

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