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LH543620P-25

1024 × 36 Synchronous FIFO

Sharp Electronics 

LH543620

1024 × 36 Synchronous FIFO

Status Flags

There are five status flags:

FF Full Flag

AF Almost-Full Flag

HF Half-Full Flag

AE Almost-Empty Flag

EF Empty Flag

The functionality and the synchronization of the status

flags are detailed in the Pins Descriptions (Functional)

section. All status flags are generated for 36-bit word

widths, not according to selected input or output port

widths.

Retransmit Mechanism

With standard FIFO operations, every data word can

be read out of the FIFO once. The Retransmit mechanism

allows reading the data more than once by providing

flexible control of the Read Pointer.

Associated with the Retransmit mechanism are three

control lines: RTMD[1:0], RT, and two Resource regis-

ters: RBASE and ROFFSET.

RTMD[1:0] sets the mode of operation. See Table 6.

RT enables the operation synchronous to CKO.

Retransmit allows three modes of operation:

Mark: RTMD[1:0] = 3 and RT is asserted. The value of

the Read Pointer is saved into the RBASE register.

Retransmit: RTMD[1:0] = 1 and RT is asserted. The

Read Pointer is loaded by the value of RBASE plus the

value of ROFFSET.

Retransmit and Mark: RTMD[1:0] = 2 and RT is as-

serted: The Read Pointer is loaded by the value of RBASE

plus the value of ROFFSET. Then the value of the Read

Pointer is saved into the RBASE register.

The timing of the retransmit is illustrated in Figures 26

and 27.

When RT is asserted and RTMD[1:0] is set to 1 or 2,

the flags change their value to indicate a ‘Retransmit

state’, i.e., EF, AE, FF deasserted; AF, HF asserted.

Three enable-read cycles are required to read the new

data word.The flags reflect the new status.The retransmit

is acknowledged even when the output is disabled

(ENO = LOW), but enable-read cycles are needed to fill

the pipeline with new information before reading the new

data.

NOTES

1. The Retransmit mechanism can be used inde-

pendently and parallel to the write operation.

2. RTMD[1:0] must be selected two cycles prior to RT

being asserted and remain stable during RT low.

3. At least two words need to be in the FIFO memory

array prior to performing a retransmit.

4. When using normal read and write operations, the FF

inhibits writing when the FIFO is full and the EF

inhibits reading when the FIFO is empty. This behav-

ior provides a protection from wraparound situations

(i.e., the Read pointer is ahead of the Write Pointer).

This protection is NOT provided when using retrans-

mit. The user should be careful not to write more than

1024 words from the marked point.

5. When the retransmit mechanism is not used, the

recommended connection is:

RTMD[1:0] = 3

RT = HIGH

The Retransmit mechanism can be useful in many

applications. For example:

1. Computer-communications applications.

When the receiver reads a block of data and finds no

errors in the data block, it can mark the beginning of

the new message by setting the FIFO in MARK mode

RTMD[1:0] = 3 and assert the RT signal for one clock

cycle.

If the receiver finds an error in the data block, it can

read the last message again by setting the FIFO in

Retransmit mode RTMD[1:0] = 1 and asserting the

RT signal for one cycle.

2. Overlap addressing for DSP applications.

A typical DSP consists of A/D-FIFO-DSP. In many

applications, the DSP needs to read a block of data

where each block overlaps the previous block (like

the overlap-and-save method for filtering.) The over-

lap addressing can be implemented by using the

LH543620 with no additional hardware as follows:

The FIFO is set to retransmit and mark mode:

RTMD[1:0] = 2, the AF offset register is programmed

to N = Block Size, and the ROFFSET register is

programmed to (N – Overlap). The data is loaded into

the FIFO each time CKin is triggered.

The DSP can sense the AF flag of the FIFO. When-

ever this flag is being asserted, a new block of data

is available in the FIFO. The DSP then reads a block

of data, and then asserts the FIFO’s RT signal, which

causes the RP and RBASE register to be set at the

beginning of the new block.

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