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MAX8772GTL

Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies

Maxim Integrated 

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1. VDD = VCC = VSHDN = VPSI = VDPRSTP = 5V, DPRSLPVR = GNDS = PGND_ = GND, VFB = VCCI = VCSP_ = VCSN_

= 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.)

PARAMETER

PWRGD, PHASEGD Startup

Delay

SYMBOL

tPWRGD

CONDITIONS

Measured at startup from the time when

CLKEN goes low

MIN TYP MAX UNITS

3

5

8

ms

CLKEN, PWRGD Threshold

CLKEN, PWRGD, PHASEGD

Delay

Measured at FB with

respect to unloaded

output voltage

Lower threshold, falling

edge (undervoltage)

-350

-300

-250

mV

15mV hysteresis (typ)

Upper threshold, rising

edge (overvoltage)

+150

+200

+250

FB forced 25mV outside the PWRGD trip

thresholds

10

µs

CLKEN, PWRGD, PHASEGD

Transition Blanking Time

tBLANK

Measured from the time when FB reaches the

target voltage based on the slew rate set by

RTIME

20

µs

PHASEGD Transition Blanking

Time

tPHASEGD

Number of DH2 pulses from when phase 2 is

enabled

32

Cycles

PHASEGD Window

Comparator Thresholds

CLKEN, PWRGD, PHASEGD

Output Low Voltage

V(CCI, FB),

0.4V ≤ V(FB) ≤ 1.5V

Lower threshold,

0.6VFB nominal

-20

15mV hysteresis (typ) Upper threshold,

-20

1.4VFB nominal

ISINK = 3mA

+20

mV

+20

0.4

V

CLKEN, PWRGD, PHASEGD

Leakage Current

High state, CLKEN, PWRGD, PHASEGD forced

to 5V

1

µA

VRHOT Trip Threshold

Measured at THRM, with respect to VCC; falling 29.5

30

30.5

%

edge, 115mV hysteresis (typ)

VRHOT Delay

VRHOT Output On-Resistance

VRHOT Leakage Current

THRM Input Leakage

tVRHOT

RVRHOT

THRM forced 25mV below the VRHOT trip

threshold; falling edge

Low state

High state. VRHOT forced to 5V

10

µs

3.5

11

Ω

1

µA

-100

+100 nA

VCC Undervoltage Lockout

Threshold

VUVLO(VCC)

Rising edge, 50mV hysteresis, DL_ pulled low

below this level

4.1

4.25 4.45

V

VCC Power-On Reset

Threshold

Falling edge, typical hysteresis = 1.1V, faults

cleared and DL_ forced high when VCC falls

1.8

V

below this level

Thermal Shutdown Threshold

TSHDN Hysteresis = 15°C

160

°C

4 _______________________________________________________________________________________

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