MF0ICU1 데이터 시트보기 (PDF) - NXP Semiconductors.
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MF0ICU1 Datasheet PDF : 31 Pages
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NXP Semiconductors
MF0ICU1
MIFARE Ultralight contactless single-ticket IC
7.5.2 Lock bytes
The bits of byte 02h and 03h of page 02h represent the field programmable read-only
locking mechanism. Each page from 03h (OTP) to 0Eh can be individually locked by
setting the corresponding locking bit Lx to logic 1 to prevent further write access. After
locking, the page becomes read-only memory.
The three least significant bits of lock byte 0 are the block-locking bits. Bit 2 deals with
pages 0Fh to 0Ah, bit 01h deals with pages 09h to 04h and bit 0 deals with page 03h
(OTP). Once the block-locking bits are set, the locking configuration for the corresponding
memory area is frozen.
MSB
LSB MSB
LSB
L
L
L
L
L BL BL BL
L
L
L
L
L
L
L
L
7
6
5
4 OTP 15-10 9-4 OTP
15 14 13 12 11 10
9
8
page 2
8 9 10 11
lock byte 0
lock byte 1
Lx locks page x to read-only
BLx blocks further locking for the memory area x
001aak570
Fig 6.
Important security: To activate the new locking configuration after a write to the lock bit area, a REQA or WUPA
command must be carried out.
Lock bytes
In Figure 6 for example if BL15-10 is set to logic 1, then bits L15 to L10 (lock byte 2
bit[7:2]) can no longer be changed.
The locking and block-locking bits are set by a WRITE command to page 2. Bytes 2 and 3
of the WRITE command, and the contents of the lock bytes are bitwise OR’ed and the
result then becomes the new contents of the lock bytes. This process is irreversible if a bit
is set to logic 1, it cannot be changed back to logic 0.
The contents of bytes 0 and 1 of page 2 are unaffected by the corresponding data bytes of
the WRITE command.
028639
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.9 — 23 July 2014
028639
© NXP Semiconductors N.V. 2014. All rights reserved.
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