ITG-3200 Product Specification
Document Number: PS-ITG-3200A-00-01.4
Revision: 1.4
Release Date: 03/30/2010
I2C Terms
Signal
S
AD
W
R
ACK
NACK
RA
DATA
P
Description
Start Condition: SDA goes from high to low while SCL is high
Slave I2C address
Write bit (0)
Read bit (1)
Acknowledge: SDA line is low while the SCL line is high at the 9th clock cycle
Not-Acknowledge: SDA line stays high at the 9th clock cycle
ITG-3200 internal register address
Transmit or received data
Stop condition: SDA going from low to high while SCL is high
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