AC82G41SLGQ3 데이터 시트보기 (PDF) - Intel

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AC82G41SLGQ3

Intel® 4 Series Chipset Family

Intel 

5.2.23 C1CYCTRKWR—Channel 1 CYCTRK WR .................................................... 144

5.2.24 C1CYCTRKRD—Channel 1 CYCTRK READ .................................................. 145

5.2.25 C1CKECTRL—Channel 1 CKE Control ....................................................... 145

5.2.26 C1REFRCTRL—Channel 1 DRAM Refresh Control........................................ 147

5.2.27 C1ODTCTRL—Channel 1 ODT Control....................................................... 149

5.2.28 EPC0DRB0—EP Channel 0 DRAM Rank Boundary Address 0 ........................ 149

5.2.29 EPC0DRB1—EP Channel 0 DRAM Rank Boundary Address 1 ........................ 150

5.2.30 EPC0DRB2—EP Channel 0 DRAM Rank Boundary Address 2 ........................ 150

5.2.31 EPC0DRB3—EP Channel 0 DRAM Rank Boundary Address 3 ........................ 150

5.2.32 EPC0DRA01—EP Channel 0 DRAM Rank 0,1 Attribute................................. 151

5.2.33 EPC0DRA23—EP Channel 0 DRAM Rank 2,3 Attribute................................. 151

5.2.34 EPDCYCTRKWRTPRE—EPD CYCTRK WRT PRE ............................................ 152

5.2.35 EPDCYCTRKWRTACT—EPD CYCTRK WRT ACT ........................................... 152

5.2.36 EPDCYCTRKWRTWR—EPD CYCTRK WRT WR ............................................. 153

5.2.37 EPDCYCTRKWRTREF—EPD CYCTRK WRT REF ............................................ 153

5.2.38 EPDCYCTRKWRTRD—EPD CYCTRK WRT READ........................................... 154

5.2.39 EPDCKECONFIGREG—EPD CKE Related Configuration Registers................... 155

5.2.40 EPDREFCONFIG—EP DRAM Refresh Configuration...................................... 156

5.2.41 TSC1—Thermal Sensor Control 1 ............................................................ 158

5.2.42 TSC2—Thermal Sensor Control 2 ............................................................ 159

5.2.43 TSS—Thermal Sensor Status .................................................................. 161

5.2.44 TSTTP—Thermal Sensor Temperature Trip Point........................................ 162

5.2.45 TCO—Thermal Calibration Offset ............................................................. 163

5.2.46 THERM1—Hardware Throttle Control ....................................................... 164

5.2.47 TIS—Thermal Interrupt Status................................................................ 165

5.2.48 TSMICMD—Thermal SMI Command ......................................................... 167

5.2.49 PMSTS—Power Management Status......................................................... 168

5.3 EPBAR............................................................................................................ 169

5.3.1 EPESD—EP Element Self Description........................................................ 169

5.3.2 EPLE1D—EP Link Entry 1 Description ....................................................... 170

5.3.3 EPLE1A—EP Link Entry 1 Address............................................................ 170

5.3.4 EPLE2D—EP Link Entry 2 Description ....................................................... 171

5.3.5 EPLE2A—EP Link Entry 2 Address............................................................ 172

6 Host-PCI Express* Registers (D1:F0)..................................................................... 173

6.1 Host-PCI Express* Register Description (D1:F0) .................................................. 175

6.1.1 VID1—Vendor Identification ................................................................... 175

6.1.2 DID1—Device Identification.................................................................... 175

6.1.3 PCICMD1—PCI Command ...................................................................... 176

6.1.4 PCISTS1—PCI Status............................................................................. 178

6.1.5 RID1—Revision Identification ................................................................. 179

6.1.6 CC1—Class Code .................................................................................. 180

6.1.7 CL1—Cache Line Size ............................................................................ 180

6.1.8 HDR1—Header Type.............................................................................. 181

6.1.9 PBUSN1—Primary Bus Number ............................................................... 181

6.1.10 SBUSN1—Secondary Bus Number ........................................................... 181

6.1.11 SUBUSN1—Subordinate Bus Number ....................................................... 182

6.1.12 IOBASE1—I/O Base Address .................................................................. 182

6.1.13 IOLIMIT1—I/O Limit Address .................................................................. 183

6.1.14 SSTS1—Secondary Status...................................................................... 183

6.1.15 MBASE1—Memory Base Address ............................................................. 184

6.1.16 MLIMIT1—Memory Limit Address ............................................................ 185

6.1.17 PMBASE1—Prefetchable Memory Base Address ......................................... 186

6.1.18 PMLIMIT1—Prefetchable Memory Limit Address......................................... 187

6.1.19 PMBASEU1—Prefetchable Memory Base Address Upper .............................. 188

6

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