WM8778SEDS/RV 데이터 시트보기 (PDF) - Wolfson Microelectronics plc
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WM8778SEDS/RV Datasheet PDF : 52 Pages
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WM8778
MASTER CLOCK TIMING
MCLK
tMCLKL
tMCLKH
tMCLKY
Production Data
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, ADC/DACMCLK = 256fs unless otherwise
stated.
PARAMETER
SYMBOL
System Clock Timing Information
ADC/DACMCLK System clock
pulse width high
tMCLKH
ADC/DACMCLK System clock
pulse width low
tMCLKL
ADC/DACMCLK System clock
cycle time
tMCLKY
ADC/DACMCLK Duty cycle
Power-saving mode activated
Normal mode resumed
Table 1 Master Clock Timing Requirements
TEST CONDITIONS
After MCLK stopped
After MCLK re-started
MIN
11
11
28
40:60
2
0.5
TYP
MAX
UNIT
1000
60:40
10
1
ns
ns
ns
µs
MCLK
cycle
Note:
If MCLK period is longer than maximum specified above, power-saving mode is entered and DACs are powered down with
internal digital audio filters being reset. In this power-saving mode, all registers will retain their values and can be accessed
in the normal manner through the control interface. Once MCLK is restored, the DACs are automatically powered up, but a
write to the volume update register bit is required to restore the correct volume settings.
DIGITAL AUDIO INTERFACE – MASTER MODE
DACBCLK
ADCBCLK
ADCLRC
WM8778
CODEC DACLRC
DOUT
DIN
DVD
Controller
Figure 2 Audio Interface - Master Mode
w
PD, Rev 4.2, July 2008
8
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