C165 데이터 시트보기 (PDF) - Infineon Technologies
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C165 Datasheet PDF : 77 Pages
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C165
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin Nr Pin Nr Input Function
TQFP MQFP Outp.
P4
IO
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits.
For a pin configured as input, the output driver is put
into high-impedance state. Port 4 can be used to
output the segment address lines:
P4.0 23 25
O
A16 Least Significant Segment Address Line
P4.1 24 26
O
A17 Segment Address Line
P4.2 25 27
O
A18 Segment Address Line
P4.3 26 28
O
A19 Segment Address Line
P4.4 29 31
O
A20 Segment Address Line
P4.5 30 32
O
A21 Segment Address Line
P4.6 31 33
O
A22 Segment Address Line
P4.7 32 34
O
A23 Most Significant Segment Address Line
RD
33 35
O
External Memory Read Strobe. RD is activated for
every external instruction or data read access.
WR/ 34 36
O
WRL
External Memory Write Strobe. In WR-mode this pin
is activated for every external data write access. In
WRL-mode this pin is activated for low byte data
write accesses on a 16-bit bus, and for every data
write access on an 8-bit bus. See WRCFG in register
SYSCON for mode selection.
READY 35 37
I
Ready Input. When the Ready function is enabled, a
high level at this pin during an external memory
access will force the insertion of memory cycle
waitstates until the pin returns to a low level.
An internal pullup device holds this pin high when
nothing is driving it.
ALE 36 38
O
Address Latch Enable Output. Can be used for
latching the address into external memory or an
address latch in the multiplexed bus modes.
EA
37 39
I
External Access Enable pin. A low level at this pin
during and after Reset forces the C165 to begin
instruction execution out of external memory. A high
level forces execution out of the internal program
memory.
“ROMless” versions must have this pin tied to ‘0’.
Data Sheet
7
V2.0, 2000-12
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