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SAA7102E/V4

Digital video encoder

NXP Semiconductors. 

Philips Semiconductors

SAA7102; SAA7103

Digital video encoder

Besides the applications for video output, the SAA7102; SAA7103 can also be used for

generating a kind of auxiliary VGA output, when the RGB non-interlaced input signal is fed

to the DACs. This may be of interest for example, when the graphics controller provides a

second graphics window at its video output port.

The basic encoder function consists of subcarrier generation, color modulation and

insertion of synchronization signals at a crystal-stable clock rate of 13.5 MHz

(independent of the actual pixel clock used at the input side), corresponding to an internal

4 : 2 : 2 bandwidth in the luminance/color difference domain. Luminance and

chrominance signals are filtered in accordance with the standard requirements of

“RS-170-A” and “ITU-R BT.470-3”.

For ease of analog post filtering the signals are twice oversampled to 27 MHz before

digital-to-analog conversion.

The total filter transfer characteristics (scaler and anti-flicker filter are not taken into

account) are illustrated in Figure 6 to Figure 11. All three DACs are realized with full 10-bit

resolution. The CR-Y-CB to RGB dematrix can be bypassed (optionally) in order to provide

the upsampled CR-Y-CB input signals.

The 8-bit multiplexed CB-Y-CR formats are “ITU-R BT.656” (D1 format) compatible, but the

SAV and EAV codes can be decoded optionally, when the device is operated in Slave

mode. For assignment of the input data to the rising or falling clock edge see

Table 28 to Table 34.

In order to display interlaced RGB signals through a euro-connector TV set, a separate

digital composite sync signal (pin HSM_CSYNC) can be generated; it can be advanced

up to 31 periods of the 27 MHz crystal clock in order to be adapted to the RGB processing

of a TV set.

The SAA7102; SAA7103 synthesizes all necessary internal signals, color subcarrier

frequency and synchronization signals from that clock.

Wide screen signalling data can be loaded via the I2C-bus and is inserted into line 23 for

standards using a 50 Hz field rate.

VPS data for program dependent automatic start and stop of such featured VCRs is

loadable via the I2C-bus.

The IC also contains closed caption and extended data services encoding (line 21), and

supports teletext insertion for the appropriate bit stream format at a 27 MHz clock rate

(see Figure 15). It is also possible to load data for the copy generation management

system into line 20 of every field (525/60 line counting).

A number of possibilities are provided for setting different video parameters such as:

• Black and blanking level control

• Color subcarrier frequency

• Variable burst amplitude etc.

SAA7102_SAA7103_4

Product data sheet

Rev. 04 — 18 January 2006

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

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