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ALC892

7.1+2 CHANNEL HD AUDIO CODEC WITH CONTENT PROTECTION

Realtek Semiconductor 

ALC892

Datasheet

7.3. Reset and Initialization

There are two types of reset within an HDA link:

• Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state

• Codec Reset. Generated by software directing a command to reset a specific codec back to its default

state

An initialization sequence is requested after any of the following three events:

• Link Reset

• Codec Reset

• Codec changes its power state (for example, hot docking a codec to an HDA system)

7.3.1. Link Reset

A link reset may be caused by 3 events:

1. The HDA controller asserts RST# for any reason (power up, or PCI reset)

2. Software initiates a link reset via the ‘CRST’ bit in the Global Control Register (GCR) of the HDA

controller

3. Software initiates power management sequences. Figure 13, shows the ‘Link Reset’ timing including

the ‘Enter’ sequence (n~r) and ‘Exit’ sequence (s~v)

Enter ‘Link Reset’:

n Software writes a 0 to the ‘CRST’ bit in the Global Control Register of the HDA controller to initiate a

link reset

o When the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at

the end of the frame

p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low

q The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state

r All link signals driven by controller and codecs should be tri-state by internal pull low resistors

7.1+2 Channel HD Audio Codec with Content Protection 19

Track ID: JATR-2265-11 Rev. 1.3

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