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T7234

Compliance with the New ETSI PSD Requirement

Agere -> LSI Corporation 

Data Sheet

January 1998

T7256 Single-Chip NT1 (SCNT1) Transceiver

Pin Information (continued)

Table 1. Pin Description (continued)

Pin Symbol Type*

Name/Function

25, 34, GNDA

40, 41

— Analog Ground. Ground leads for analog circuitry.

26

RNR

I Receive Negative Rail for S/T-Interface. Negative input of S/T-interface analog re-

ceiver. Connect to transformer through a 10 kΩ ± 10% resistor.

27

RPR

I Receive Positive Rail for S/T-Interface. Positive input of S/T-interface analog re-

ceiver. Connect to transformer through a 10 kΩ ± 10% resistor.

28 VRCM — Common-Mode Voltage Reference for U-Interface Circuits. Connect a

0.1 µF ± 20% capacitor to GNDA (as close to the device pins as possible).

29

VRP

— Positive Voltage Reference for U-Interface Circuits. Connect a 0.1 µF ± 20% ca-

pacitor to GNDA (as close to the device pins as possible).

30

VRN

— Negative Voltage Reference for U-Interface Circuits. Connect a 0.1 µF ± 20% ca-

pacitor to GNDA (as close to the device pins as possible).

31

HN

I Hybrid Negative Input for U-Interface. Connect directly to negative side of

U-interface transformer.

32

LOP

O Line Driver Positive Output for U-Interface. Connect to the U-interface transformer

through a 16.9 Ω ± 1% resistor.

35

LON

O Line Driver Negative Output for U-Interface. Connect to the U-interface transform-

er through a 16.9 Ω ± 1% resistor.

36

HP

I Hybrid Positive Input for U-Interface. Connect directly to positive side of

U-interface transformer.

37 SDINN

I Sigma-Delta A/D Negative Input for U-Interface. Connect via an 820 pF ± 5%

capacitor to SDINP.

38 SDINP

I Sigma-Delta A/D Positive Input for U-Interface. Connect via an 820 pF ± 5%

capacitor to SDINN.

43 RESET Id Reset (Active-Low). Asynchronous Schmitt trigger input. Reset halts data transmis-

sion, clears adaptive filter coefficients, resets the U-transceiver timing recovery cir-

cuitry, resets the S/T-interface transceiver, and sets all microprocessor register bits

to their default state. During reset, the U-interface transmitter produces 0 V and the

output impedance is 135 Ω at tip and ring. The RESET pin can be used to implement

quiet mode maintenance testing (refer to pin 2 for more description). The states of

pins 11, 12, and 15 (ACTMODE/INT, SYN8K_CTL/SDI, and AUTOACT/SCK, respec-

tively) are latched on the rising edge of RESET. (See corresponding pin descriptions.)

An internal 100 kΩ pull-down resistor is on this pin. RESET must be held low for

1.5 ms after power on. Device is fully functional after an additional 1 ms.

44 HIGHZ Iu High-Impedance Control (Active-Low). Control of the high-impedance function. An

internal 100 kΩ pull-up resistor is on this pin. Note: This pin does not 3-state the an-

alog outputs.

0—All digital outputs enter high-impedance state.

1—No effect on device operation.

* Iu = input with internal pull-up; Id = input with internal pull-down.

Lucent Technologies Inc.

9

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