SDA9362 데이터 시트보기 (PDF) - Siemens AG
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SDA9362 Datasheet PDF : 39 Pages
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SDA 9362
2
System Description
2.1 Functional Description
The main input signals are HSYNC with doubled horizontal frequency, VSYNC with
vertical frequencies of 50/100 Hz or 60/120 Hz and the line locked clock CLL.
The output signals control the horizontal as well as the vertical deflection stages and the
East-West raster correction circuit.
The H-output signal HD compensates the delays of the line output stage and its phase
can be modulated vertical frequent to remove horizontal distortions of vertical raster lines
(V-Bow, V-Angle). Time reference is the middle of the front and back edge of the line
flyback pulse. A positive HD pulse switches off the line output transistor. Maximal H-shift
is 2.25 µs.
Picture tubes with 4:3 or 16:9 aspect ratio can be used by adapting the raster to the
aspect ratio of the source signal.
The V-output sawtooth signals VD- and VD+ controls a DC coupled output stage and can
be disabled. Suitable blanking signals are delivered by the IC.
The East-West output signal E/W is a vertical frequent parabola of 4th order, enabling
an additional corner correction, separately for the upper and lower part.
Two Ι2C Bus controlled digital outputs are available for general purpose.
The picture width and picture height compensation (PW/PH Comp) processes the beam
current dependent input signal IBEAM with effect to the outputs E/W and VD to keep
width and height constant and independent of brightness.
The alignment parameter Horizontal Shift Compensation enables to adjust the influence
of the input signal IBEAM on the horizontal phase.
The selectable start up circuit controls the energy supply of the H-output stage during the
receiver's run up time by smooth decreasing the line output transistors switching
frequency down to the normal operating value (softstart). HD starts with about 55 kHz
and converges within 85 ms to its final value. The high time is kept constant. The normal
operating pulse ratio H/L is 45/55. A watch dog function limits the period of the HD output
signal independent of the clock CLL to max 35.2 µs.
The protection circuit watches an EHT reference and the sawtooth of the vertical output
stage. H-output stage is switched off if the EHT succeeds a defined threshold or if the
V-deflection fails (refer to page 36). The function of this circuit is based on the internal
quartz oscillator and therefore independent of the input clock CLL.
HPROT: Input
Vi < V2
Vi > V1
V2 ≤ Vi < V1
Continues blanking
HD disabled
Operating range
Semiconductor Group
10
1998-02-01
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