CDB4225 데이터 시트보기 (PDF) - Cirrus Logic
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CDB4225 Datasheet PDF : 30 Pages
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SWITCHING CHARACTERISTICS - CONTROL PORT
(TA = 25oC VD+, VA+ = 5V±10%; Inputs: logic 0 = DGND, logic 1 = VD+, CL = 30pF)
Parameter
Symbol
Min
SPI Mode (H/S=0)
CCLK Clock Frequency
fsck
0
CS High Time Between Transmissions
tcsh
1.0
CS Falling to SCK Edge
tcss
20
CCLK Low Time
tscl
500
CCLK High Time
tsch
500
CDIN to CCLK Rising Setup Time
tdsu
250
CCLK Rising to DATA Hold Time
CDIN (Note 9)
tdh
50
CCLK Falling to CDOUT stable
tpd
Rise Time of CDOUT
tr1
Fall Time of CDOUT
tf1
Rise Time of CCLK and CDIN
tr2
Fall Time of CCLK and CDIN
tf2
Notes: 9. Data must be held for sufficient time to bridge the transition time of CCLK.
CS4225
Max
Units
1
MHz
µs
ns
ns
ns
ns
ns
250
ns
25
ns
25
ns
100
ns
100
ns
CS
t css
t scl t sch
t csh
CCLK
t r2
t f2
CDIN
CDOUT
t dsu t dh t pd
6
DS86PP8
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