MU9C1480A 데이터 시트보기 (PDF) - Unspecified
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MU9C1480A Datasheet PDF : 28 Pages
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MU9C1480A/L Draft
OPERATIONAL CHARACTERISTICS Continued
instructions are active only for one Command Read or
Write cycle after being loaded into the Instruction decoder.
return to a foreground network filtering task from a
background housekeeping task.
The data and control interfaces to the LANCAM are
synchronous. During a Write cycle, the Control and Data
inputs are registered by the falling edge of /E. When writing
to the persistently selected data destination, the
Destination Segment counter is clocked by the rising edge
of /E. During a Read cycle, the Control inputs are registered
by the falling edge of /E, and the Data outputs are enabled
while /E is LOW. When reading from the persistently
selected data source, the Source Segment counter is
clocked by the rising edge of /E.
THE REGISTER SET
The Control, Segment Control, Address, Mask Register 1,
and the Persistent Source and Destination registers are
duplicated, with one set termed the Foreground set and
the other the Background set. The active set is chosen by
issuing Select Foreground Registers or Select Background
Registers instructions. By default, the Foreground set is
active after a reset. Having two alternate sets of registers
that determine the device configuration allows for a rapid
Writing a value to the Control register or writing data to the
last segment of the Comparand or either mask register will
cause an automatic comparison to occur between the
contents of the Comparand register and the words in the
CAM segments of the memory marked valid, masked by
MR1 or MR2 if selected in the Control register.
Instruction Decoder
The Instruction decoder is the write-only decode logic for
instructions and is the default destination for Command
Write cycles. If an instruction’s Address Field flag (bit 11)
is set to a 1, it is a two-cycle instruction that is not executed
immediately. For the next cycle only, the data from a
Command Write cycle is loaded into the Address register
and the instruction then completes at that address. The
Address register will then increment, decrement, or stay at
the same value depending on the setting of Control Register
bits CT3 and CT2. If the Address Field flag is not set, the
memory access occurs at the address currently contained
in the Address register.
16
D Q15–0
/E
/W
/C M
/EC
D Q15–0
/E
/W
/C M
L AN C AM
/EC
/MI
/ FI
/ FF
/MF
Vcc
D Q15–0
/E
/W
/C M
L AN C AM
/EC
/MI
/ FI
/ FF
/MF
D Q15–0
/E
/W
/C M
L AN C AM
/EC
/MI
/ FI
/ FF
/MF
S YS TE M F U L L
S YS TE M MATC H
Figure 1a: Vertical Cascading
7
V cc
/MI
LANCAM
/MA
PLD
/MI
LANCAM
/MA
/MI
LANCAM
/MA
/MI
LANCAM
/MA
S Y S TE M
M ATCH
Figure 1b: External Prioritizing
Rev. 3.0 Draft
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