HD74CDC2509BTEL 데이터 시트보기 (PDF) - Renesas Electronics

부품명

상세내역

일치하는 목록

HD74CDC2509BTEL

3.3-V Phase-lock Loop Clock Driver

Renesas Electronics 

HD74CDC2509B

Switching Characteristics

(CL = 30 pF, Ta = 0 to 85°C)

Item

Symbol

VCC = 3.3 V±0.3 V

Min

Typ

Max

Unit From (Input) To (Output)

Phase error time

Between output pins skew *1

tpe

–150

—

150

ps 66 MHz < FBIN↑

CLKIN↑ ≤

100 MHz

tsk (O)

—

—

200

ps Any Y or Any Y or

FBOUT,

FBOUT

F (clkin =

100 MHz)

Cycle to cycle jitter

–100

—

100

ps F (clkin = Any Y or

100 MHz) FBOUT

Duty cycle

45

—

55

% F (clkin = Any Y or

100 MHz) FBOUT

Output rise / fall time

tTLH

5.0

—

1.0

volts/ns

Any Y or

FBOUT

tTHL

5.0

—

1.0

Analog power supply rejection

Vapsr *2

100

—

(DC to 10 MHz)

—

mVP–P

Any Y or

FBOUT

AVCC

Notes: The specifications for parameters in this table are applicable only after any appropriate stabilization time has

elapsed.

1. The tsk(O) specification is only valid for equal loading of all outputs.

2. This parameter is characterized but not tested.

Timing Requirements

Item

Symbol Min

Max

Unit

Test Conditions

Input clock frequency

fclock

50

125

MHz

Input clock duty cycle

Stabilization time *1

40

60

%

—

1

ms After power up

Note: 1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal.

In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at

CLK. Until phase lock is obtained, the specifications for propagation delay and skew parameters given in the

switching characteristics table are not applicable.

Test Circuit

From output

under test

*1

CL= 30 pF

500 Ω

Note: 1. CL includes probe and jig capacitance.

Rev.9.00 Apr 07, 2006 page 5 of 7

Share Link: