AA121XK01 데이터 시트보기 (PDF) - Unspecified
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AA121XK01 Datasheet PDF : 25 Pages
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6. INTERFACE TIMING
LVDS transmitter input signal
(1) Timing Specifications
ITEM
SYMBOL MIN.
TYP.
MAX.
UNIT
Frequency
DCLK Period
Active Time
fCLK
tCLK
tHA
50
12.5
1024
65
15.4
1024
80
20
1024
MHz
ns
tCLK
Blanking Time
tHB
20
320
--
tCLK
Horizontal
Frequency
fH
42.4
48.4
60
kHz
DENA
Period
tH
16.6
20.7
23.6
μs
Active Time
tVA
768
768
768
tH
Blanking Time
tVB
3
38
--
tH
Vertical
Frequency
fV
55
60
75
Hz
Period
tV
13.3
16.7
18.2
ms
[Note]
1) DENA (Data Enable) should always be positive polarity as shown in the timing specification.
2) DCLK should appear during all invalid period.
3) LVDS timing follows the timing specifications of LVDS receiver IC: THC63LVDF84B(Thine).
4) In case of blanking time fluctuation, please satisfy following condition.
tVBn > tVBn-1 − 3(tH)
MITSUBISHI
(9/24)
AA121XK01_02_00
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