IDT7024S15PF 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT7024S15PF

HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7024S/L

HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (6)

Symbol

Parameter

IDT7024X15

Com'l Only

Min. Max.

IDT7024X17

Com'l Only

Min. Max.

BUSY TIMING (M/S = VIH)

tBAA

BUSY Access Time from Address Match

—

15

—

17

tBDA

BUSY Disable Time from Address Not Matched —

15

—

17

tBAC

BUSY Access Time from Chip Enable Low

—

15

—

17

tBDC

tAPS

tBDD

tWH

BUSY Disable Time from Chip Enable High

Arbitration Priority Set-up Time(2)

BUSY Disable to Valid Data(3)

Write

Hold

After

(5)

BUSY

—

15 —

17

5

—

5

—

—

18

—

18

12

— 13

—

BUSY TIMING (M/S = VIL)

tWB

BUSY Input to Write(4)

tWH

Write

Hold

After

(5)

BUSY

0

—

0

—

12

—

13

—

PORT-TO-PORT DELAY TIMING

tWDD

Write Pulse to Data Delay(1)

tDDD

Write Data Valid to Read Data Delay(1)

—

30

—

30

—

25

—

25

IDT7024X20

Min. Max.

—

20

—

20

—

20

—

17

5

—

—

30

15

—

0

—

15

—

—

45

—

35

IDT7024X25

Min. Max.

—

20

—

20

—

20

—

17

5

—

—

30

17

—

0

—

17

—

—

50

—

35

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Symbol

Parameter

BUSY TIMING (M/S = VIH)

tBAA

BUSY Access Time from Address Match

tBDA

BUSY Disable Time from Address Not Matched

tBAC

BUSY Access Time from Chip Enable Low

tBDC

tAPS

tBDD

tWH

BUSY Disable Time from Chip Enable High

Arbitration Priority Set-up Time(2)

BUSY Disable to Valid Data(3)

Write

Hold

After

(5)

BUSY

IDT7024X35

Min. Max.

IDT7024X55

Min. Max.

IDT7024X70

Mil. Only

Min. Max. Unit

—

20

—

45

—

45 ns

—

20

—

40

—

40 ns

—

20

—

40

—

40 ns

—

20

—

35

—

35 ns

5

—

5

—

5

— ns

—

35

—

40

—

45 ns

25

—

25

—

25

— ns

BUSY TIMING (M/S = VIL)

tWB

BUSY Input to Write(4)

tWH

Write

Hold

After

(5)

BUSY

0

—

0

—

0

— ns

25

—

25

—

25

— ns

PORT-TO-PORT DELAY TIMING

tWDD

tDDD

Write Pulse to Data Delay(1)

Write Data Valid to Read Data Delay(1)

—

60

—

80

—

95 ns

—

45

—

65

—

80 ns

NOTES:

2740 tbl 15

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VIH)" or "Timing Waveform

of Write With Port-To-Port Delay (M/S = VIL)".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual), or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention with port "A".

5. To ensure that a write cycle is completed on port "B" after contention with port "A".

6. "X" in part numbers indicates power rating (S or L).

6.15

12

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