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PCK2057DGG

70 – 190 MHz I2C differential 1:10 clock driver

NXP Semiconductors. 

Philips Semiconductors

70 – 190 MHz I2C differential 1:10 clock driver

Product data

PCK2057

ABSOLUTE MAXIMUM RATINGS (see Note 1)

Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

MIN

MAX

UNIT

VDDQ/AVDD Supply voltage range

0.5

3.6

V

VDDI2C

I2C supply voltage range

0.5

4.6

V

except SCL and SDA

VI

Input voltage range

SCL and SDA

see Notes 2 and 3

see Notes 2 and 3

–0.5

VDDQ + 0.5

V

–0.5

VDDI2C + 0.5

V

VO

Output voltage range

see Notes 2 and 3

–0.5

VDDQ + 0.5

V

IIK

Input clamp current

VI < 0 or VI > VDDQ

—

±50

mA

IOK

Output clamp current

VO < 0 or VO > VDDQ

—

±50

mA

IO

Continuous output current

VO = 0 to VDDQ

—

±50

mA

Continuous current to GND or VDDQ

—

±100

mA

Tstg

Storage temperature range

–65

+150

°C

NOTES:

1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”

is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

3. This value is limited to 3.6 V maximum.

RECOMMENDED OPERATING CONDITIONS (see Note 1)

SYMBOL

PARAMETER

TEST

CONDITIONS

MIN

LIMITS

TYP

MAX

UNIT

Supply voltage

VDDQ

2.3

AVDD

2.2

VDDI2C

see Note 2

2.3

CLK, CLK,

HCSL buffer only

—

—

2.7

V

—

2.7

V

—

3.6

V

0

0.24

V

VIL

LOW-level input voltage CLK, CLK

FBIN, FBIN

SDA, SCL

CLK, CLK,

HCSL buffer only

–0.3

—

—

0.66

—

—

—

0.71

VDDQ – 0.4

V

VDDQ/2 – 0.18

V

0.3 × VDDI2C

V

—

V

VIH

HIGH-level input voltage CLK, CLK

FBIN, FBIN

SDA, SCL

0.4

—

VDDQ/2 + 0.18

—

0.7 × VDDI2C

—

VDDQ + 0.3

V

—

V

—

V

DC input signal voltage

see Note 3

–0.3

—

VDDQ + 0.3

V

VID

Differential input signal

voltage

DC: CLK, FBIN

AC: CLK, FBIN

see Note 4

see Note 4

0.36

0.2

—

VDDQ + 0.6

V

—

VDDQ + 0.6

V

VIX

Input differential pair cross-voltage

see Note 5 0.45 × (VIH – VIL)

—

0.55 × (VIH – VIL)

V

IOH

HIGH-level output current

—

—

–12

mA

IOL

LOW-level output current

SDA

—

—

12

mA

—

—

3

mA

SR

Input slew rate

see Figure 3

1

—

4

V/ns

SSC modulation frequency

30

—

33.3

kHz

SSC clock input frequency deviation

0

—

–0.50

%

Tamb

Operating free-air temperature

0

—

+70

°C

NOTES:

1. Unused inputs must be held HIGH or LOW to prevent them from floating.

2. All devices on the I2C-bus, with input levels related to VDDI2C, must have one common supply line to which the pull-up resistor is connected.

3. DC input signal voltage specifies the allowable DC execution of differential input.

4. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level, and VCP

is the complementary input level.

5. Differential cross-point voltage is expected to track variations of VDD and is the voltage at which the differential signals must be crossing.

2001 Jun 12

6

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