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AS8E32K32

32K x 32 EEPROM

Austin Semiconductor 

AUSTIN SEMICONDUCTOR, INC.

AS8E32K32

32K x 32 EEPROM

DEVICE OPERATION

The 32Kx 32 EEPROM memory soultion is an electricaly erasable and programmable memory module that is accessed like a

Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte-page register to

allow writing of up to 64 bytes of data simultaneously. During a write cycle, the address and 1 to 64 bytes of data are internally

latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically

write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end

of a write cycle has been detected a new access for a read or write can begin.

READ

The memory module is accessed like a Static RAM. When

CE\ and OE\ are low and WE\ is High, the data stored at the

memory location determined by the address pins is asserted on

the outputs. The module can be read as a 32 bit, 16 bit or 8 bit

device. The outputs are put in the high impedance state when

either CE\ or OE\ is high. This dual-line control gives designers

flexibility in preventing bus contention in their system.

BYTE WRITE

A low pulse on the WE\ or CE\ input with CE\ or WE\ low

(respectively) and OE\ high initiates a write cycle. The address is

latched on the falling edge of CE\ or WE\, whichever occurs last.

The data is latched by the first rising edge of CE\ or WE\. Once a

BWDW (byte, word or double word) write has been started it

will automatically time itself to completion.

PAGE WRITE

The page write operation of the 32K x 32 EEPROM allows

1 to 64 BWDWs of data to be written into the device during a

single internal programming period. Each new BWDW must be

written within 150-µs (tBLC) of the previous BWDW. If the

tBLC limit is exceeded the device will cease accepting data and

commence the internal programming operation. For each WE

high to low transition during the page write operation, A6-A14

must be the same.

The A0-A5 inputs are used to specify which bytes within

the page are to be written. The bytes may be loaded in any order

and may be altered within the same load period. Only bytes

which are specified for writing will be written; unnecessary

cycling of other bytes within the page does not occur.

DATA POLLING

this memory module features DATA Polling to indicate the

end of a write cycle. During a byte or page write cycle an

attempted read of the last byte written will result in the comple-

ment of the written data to be presented on I/O7. Once the write

cycle has been completed, true data is valid on all outputs, and

the next write cycle may begin. DATA Polling may begin at

anytime during the write cycle.

TOGGLE BIT

In addition to DATA Polling the module provides another

method for determining the end of a write cycle. During the write

operation, successive attempts to read data from the device will

result in I/O6 of the accessed die toggling between one and zero.

Once the write has completed, I/O6 will stop toggling and valid

data will be read. Reading the toggle bit may begin at any time

during the write cycle.

DATA PROTECTION

If precautions are not taken, inadvertent writes may occur

during transitions of the host power supply. The E2 module has

incorporated both hardware and software features that will

protect the memory against inadvertent writes.

HARDWARE PROTECTION

Hardware features protect against inadvertent writes to the

module in the following ways: (a) VCC sense - if VCC is below

3.8 V (typical) the write function is inhibited; (b) VCC power-on

delay - once VCC has reached 3.8 V the device will automatically

time out 5 ms (typical) before allowing a write; (c) write inhibit -

holding any one of OE\ low, CE\ high or WE\ high inhibits write

cycles; (d) noise filter - pulses of less than 15 ns (typical) on the

WE\ or CE\ inputs will not initiate a write cycle.

SOFTWARE DATA PROTECTION

A software controlled data protection feature has been

implemented on the memory module. When enabled, the

software data protection (SDP), will prevent inadvertent writes.

The SDP feature may be enabled or disabled by the user and is

shipped with SDP disabled.

SDP is enabled by the host system issuing a series of thre e

write commands; three specific bytes of data are written to three

specific addresses (refer to Software Data Protection Algorithm).

After writing the three byte command sequence and after tWC

the entire module will be protected from inadvertent write

operations. It should be noted, that once protected the host may

still perform a byte of page write to the module. This is done by

preceding the data to be written by the same three byte command

sequence used to enable SDP.

Once set, SDP will remain active unless the disable

command sequence is issued. Power transitions do not disable

SDP and SDP will protect the 32K x 32 EEPROM module during

power-up and Power-down conditions. All command sequences

must conform to the page write timing specifications. The data

in the enable and disable command sequences is not written to the

device and the memory addresses used in the sequence may be

written with data in either a byte of page write operation.

After setting SDP, any attempt to write to the device

without the three byte command sequence will start the internal

write timers. No data will be written to the device; however, for

the duration of tWC, read operations will effectively be polling

operations.

AS8E32K32

REV. 1.5 9/99

2

Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.

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