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MK50H25

HIGH SPEED LINK LEVEL CONTROLLER

STMicroelectronics 

3.1 Functional Blocks

Refer to the block diagram in Figure 2.

The MK50H25 is primarily initialized and control-

led through six 16-bit Control and Status Regis-

ters (CSR0 thru CSR5). The CSR’s are accessed

through two bus addressable ports, the Register

Address Port (RAP), and the Register Data Port

(RDP). The MK50H25 may also generate an in-

terrupt(s) to the Host. These interrupts are en-

abled and disabled through CSR0.

The on-chip microcontroller is used to control the

movement of parallel receive and transmit data,

and to handle the Address field filtering.

3.1.1 Microcontroller

The microcontroller controls all of the other blocks

of the MK50H25. The microcontroller performs

frame processing and protocol processing. All

primitive processing and generation is also done

here. The microcode ROM contains the control

program of the microcontroller.

3.1.2 Receiver

Serial receive data comes into the Receiver (Fig-

ure 2). The Receiver is responsible for:

1. Leading and trailing flag detection.

2. Deletion of zeroes inserted for transparency.

3. Detection of idle and abort sequences.

4. Detection of good and bad FCS (CRC).

5. Monitoring Receiver FIFO status.

6. Detection of Receiver Over-Run.

7. Odd byte detection.

NOTE: If frames are received that have an odd

number of bytes then the last byte of the

frame is said to be an odd byte.

8. Detection of non-octet aligned frames. Such

frames are treated as invalid (CCITT X.25 sec

2.3.5.3)

3.1.3 Transmitter

The Transmitter is responsible for:

1. Serialization of outgoing data.

2. Generating and appending the FCS (CRC).

3. Framing outgoing frame with flags.

4. Zero bit insertion for transparency.

5. Transmitter Under-Run detection.

6. Transmission of odd byte.

7. RTS/CTS control.

3.1.4 Frame Check Sequence or Cyclic

Redundancy Check

The FCS (CRC) on the transmitter or receiver

MK50H25

may be either 16 bit or 32 bit, and is user select-

able. For full duplex operation, both the receiver

and transmitter have individual FCS computation

circuits. The characteristics of the FCS are:

Transmitted Polarity: Inverted

Transmitted Order: High Order Bit First

Pre-set Value: All 1’s

Polynomial 16 bit:

X16 + X12 + X5 + 1

Remainder 16 bit (if received correctly):

High order bit-->0001 1101 0000 1111

Polynomial 32 bit:

X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +

X8 + X7 + X5 + X4 + X2 + X + 1

Remainder 32 bit (if received correctly):

high order bit--> 1100 0111 0000 0100

1101 1101 0111 1011

3.1.5 Receive FIFO

The Receive FIFO buffers the data received by

the receiver. This performs two major functions.

First, it resynchronizes the data from the receive

clock to the system clock. Second, it allows the

microcontroller time to finish whatever it may be

doing before it has to process the received data.

The receive FIFO holds the data from the receiver

without interrupting the microcontroller for service

until it contains enough data to reach the water-

mark level, or an end of frame is received. This

watermark level can be programmed in CSR4

(FWM) to occur when the FIFO contains at least

18 or more bytes; 34 or more bytes; or 50 or

more bytes. This programmability , along with the

programmable burst length of the DMA controller,

enables the user to define how often and for how

long the MK50H25 must use the host bus. For

more information, see CSR4.

For example, if the watermark level is set at 34

bytes and the burst length is limited to 8 word

transfers at a time, the MK50H25 will request

control of the host bus as soon as 34 bytes are

received and again after every 16 subsequent

bytes.

3.1.6 Transmit FIFO

The Transmit FIFO buffers the data to be trans-

mitted by the MK50H25. This also performs two

major functions. First, it resynchronizes the data

from the system clock to the transmit clock. Sec-

ond, it allows the microcontroller and DMA con-

troller to burst read data from the host’s memory

buffers; making both the MK50H25 and the host

bus more efficient.

The transmit FIFO has a watermark scheme simi-

lar to the one described for the receive FIFO

above, and uses the same FWM value selections

in CSR4 for the watermark. Once filled to within

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