MK50H25 데이터 시트보기 (PDF) - STMicroelectronics
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MK50H25 Datasheet PDF : 62 Pages
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MK50H25
4.2.1 Mode Register
The Mode Register allows alteration of the MK50H25’s operating parameters.
IADR + 00
1111110000000000
5432109876543210
MFS
<4:0>
E
X
T
C
F
E
X
T
A
F
D
A
C
E
E
X
T
C
E
X
T
A
D
R
F
C
S
D
T
F
C
S
F
C
S
S
LBACK
<2:0>
BIT NAME
15:11 MFS<4:0>
DESCRIPTION
Minimum Frame Spacing defines the minimum number of flag
sequences transmitted between adjacent frames transmitted by the
MK50H25. This only affects frames transmitted by the MK50H25
and does not restrict the spacing of the frames received by the
MK50H25. When using RTS/CTS control this field defines the
number of flags transmitted at the beginning of the frame after
CTS is driven low (minus one for the trailing flag). See the following
table for encoding of this field.
NUMBER OF FLAGS
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
MFS<4:0>
1
0
2
4
9
18
5
11
22
12
25
19
7
15
31
30
NUMBER OF FLAGS
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
MFS<4:0>
28
24
17
3
6
13
27
23
14
29
26
21
10
20
8
16
10 EXTCF
09 EXTAF
08
DACE
07 EXTC
06 EXTA
05 DRFCS
Extended Control Force. If set along with EXTC, the receiver will assume
the control field to be two octets long regardless of the first two bits of
the control field. See EXTC below.
Extended Address Force. If set along with EXTA, the receiver will
assume the address to be two otets long regardless of the first bit of
the address. See EXTA below.
Address and control field extraction are disabled when DACE is set
Address and control fields are treated as data and placed in memory
as such. DACE must be written with "1" for normal transparent data
transfer operation, but can be set to "0" for doing address and control
field filtering.
Extended Control Field filtering is enabled when EXTC = 1 if DACE = 0
and PROM = 0 (PROM is in CSR2).
Extended Address Field filtering is enabled when EXTA = 1 if DACE = 0
and PROM = 0 (PROM is in CSR2).
Disable Receiver FCS (CRC). When DRFCS = 0, the receiver will extract
and check the FCS field at the end of each frame. When DRFCS = 1,
the receiver continues to extract the last 16 or 32 bits of each frame,
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