MK50H25 데이터 시트보기 (PDF) - STMicroelectronics
부품명
상세내역
제조사
MK50H25 Datasheet PDF : 62 Pages
| |||
MK50H25
07:00
IADR
The high order 8 bits of the address of the first word (lowest address)
in the Initialization Block. IADR must be written by the Host prior to
issuing an INIT primitive.
4.1.2.4 Control and Status Register 3 (CSR3)
RAP<3:1> = 3
1111110000000000
5432109876543210
IADR <15:00>
0
BIT
NAME
DESCRIPTION
15:00
IADR
The low order 16 bits of the address of the first word (lowest address)
in the Initialization Block. Must be written by the Host prior to issuing
an INIT primitive. The Initialization block must begin on an even byte
boundary.
4.1.2.5 Control and Status Register 4 (CSR4)
CSR4 allows redefinition of the bus master interface.
RAP<3:1> = 4
1111110000000000
5432109876543210
X XR R RX
W WW W O H
D DD D BO
1 01 0 AL
D
F
W
M
B
A
E
B
U
S
R
BB
SU
WR
PS
CT
1
:
0
BA
S
W
C
O
P
D
N
B
C
O
N
BIT NAME
15:12 XWD0/1, RWD0/1
11 ROBA
10 XHOLD
22/62
DESCRIPTION
These bits enable and determine the timer values for the Transmit and
Receive Watchdog Timers. These timers are independently program-
mable and are reset by any transition on the TCLK and RCLK pins re-
spectively. The Watchdog timers will expire after approximately Wn
SYSCLK cycles (if not reset by transition on TCLK / RCLK pins) and
Provider Primitive 3 will be issued. The following table shows the se-
lections for Wn:
XWD1/RWD1
0
0
1
1
XWD0/RWD0
0
1
0
1
Wn
Disabled
218
219
220
Setting this bit will cause the MK50H25 to put the first byte of received
data into both the upper and lower bytes of the receive buffer to effec-
tively cause the Receive data to be Odd-Byte Aligned. This feature is
particularly useful for extraction of odd-byte Level 3 headers from re-
ceived frames leaving the remaining data even byte aligned.
Setting this bit enables the Transmit FIFO Hold-off mechansim of the
MK50H25. The Transmit FIFO Hold-off watermark is selected along
with the FIFO watermark so as to avoid possible conflicts.
Share Link: 