MK50H25(1994) 데이터 시트보기 (PDF) - STMicroelectronics
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MK50H25 Datasheet PDF : 64 Pages
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MK50H25
01 ACON
00 BCON
ALE CONTROL defines the assertive state of pin 18 when the
MK50H25 is a Bus Master. ACON is READ/ WRITE and cleared by
Bus RESET.
ACON
0
1
PIN18
ASSERTED HIGH
ASSERTED LOW
NAME
ALE
AS
BYTE CONTROL redefines the Byte Mask and Hold I/O pins.
BCON is READ/WRITE and cleared by Bus RESET.
BCON
0
1
PIN16
BM1
B USA K O
PIN15
BM0
BYTE
PIN17
HOLD
BUSRQ
4.1.2.6 Control and Status Register 5 (CSR5)
CSR5 facilitates control and monitoring of modem controls.
RAP<3:1> = 5
1111110000000000
5432109876543210
00
0
0
0
0
0
0
0
0
X
E
D
R
T
S
D
T
D
S
D
T
D
S
GE RRRR
ENDD
BIT
15:06
5
NAME
0
XEDGE
4
RTSEN
3
DTRD
2
DSRD
1
DTR
24/64
DESCRIPTION
Reserved, must be written as zeroes.
Setting this bit causes the TD output to change on the rising edge of
TCLK rather than on the falling edge as indicated in the description of
pin 25. This may be useful at high TCLK rates where internal delays
may cause application required TD to TCLK setup times to otherwise
be violated.
RTS/CTS ENABLE is a READ/WRITE bit used to configure pins 26
and 30. If this bit is set, pin 26 becomes RTS and pin 30 becomes
CTS. RTS is driven low whenever the MK50H25 has data to trans-
mit and is kept low during transmission. RTS will be driven high
after the closing flag of a signal unit is transmited if either no other
frames are in the FIFO or if the minimum signal unit spacing is higher
than 2 (see Mode Register). The MK50H25 will not begin transmission
and TD will remain HIGH if CTS is high. If RTSEN = 0 then pins 26
and 30 become programmable I/O pins DTR and DSR. The direction
and behavior of DSR and DTR are controlled by the following bits.
DTR DIRECTION is a READ/WRITE bit used to control the direction
of the DTR/RTS pin. If DTRD = 0, the DTR/RTS pin becomes an input
pin and the DTR bit reflects the current value of the pin; if DTRD = 1,
the DTR/RTS pin is an output pin controlled by the DTR bit below.
DSR DIRECTION is a READ/WRITE bit used to control the direction
of the DSR/CTS pin. If DSRD = 0, the DSR/CTS pin becomes an input
pin and the DSR bit reflects the current value of the pin; if DSRD = 1,
the DSR/CTS pin is an output pin controlled by the DSR bit below.
DATA TERMINAL READY is used to control or observe the DTR I/O
pin depending on the value of DTRD. If DTRD = 0, this bit be-
comes READ ONLY and always equals the current value of the
DTR/RTS pin. If DTRD = 1, this bit becomes READ/WRITE and
any value written to this bit appears on the DTR/RTS pin.
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