M3488B1 데이터 시트보기 (PDF) - STMicroelectronics

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M3488B1

256 x 256 DIGITAL SWITCHING MATRIX

STMicroelectronics 

M3488

PIN DESCRIPTION

D7 to D0

Data bus pins. The bidirectional bus is usedto trans-

fer dataand instructions to/fromthe microprocessor.

D0 is the least significant digit. The output bus is 8

bits wide ; input is only 5 bits wide. (D4 to D0)

The bus is tristate and cannot be used while RESET

is held low.

The meaning of input data, such as bus or channel

numbers, and of expected output data is specified

in detail by the instruction description. (Pagg. 12-14)

C/D (pin 30)

Input control pin, select pin. In a write operation

C/D = 0 qualifies any bus content as data, while

C/D = 1 qualifies it as an opcode. In a read operation

OR1 is selected by C/D = 0, OR2 by C/D = 1.

A1, S1, A2, S2

Address select or match pins. In a multi-chip con-

figuration (e.g. a single stage matrix expansion), us-

ing the same CS pins, the match condition (A1 = S1

and A2 = S2) leaves the commandinstruction as de-

fined; on the contrary the mismatch condition modi-

fies the execution as follows : instructions 1 and 3

are reversed to channeldisconnection, instruction 5

is unaffected, instructions 2-4-6 are cancelled (not

executed).

Bus reading takes place only on match condition,

instruction flow is in any case affected.

Eachpins couple is commutative : in a multichip con-

figuration pins S1 and S2 give a hard-wired address

selection for individual matrixes, while in single con-

figuration S1 and A1 or S2 and A2 are normally

tied together.

CS1, CS2

Commutative chip select pins. They enable the de-

vice to perform valid read/write operations (active

low). Two pins allow row/column selection with dif-

ferent types of microprocessors ; normally one is

tied to ground.

WR

Pin WR, when CS1 and CS2 are low, enables data

transfer from microprocessor to the device. Data or

opcode and controls are latchedon WR rising edge.

Becauseof internal clock resynchronizationone sin-

gle additionalrequirement is recommended in order

to produce a simultaneous instruction execution in

a multichip configuration: WR rising edge has to be

20 to 20 + tWL(CK) nsec late relative to clock falling

edge.

RD

When CS1 andCS2 are low and match condition ex-

ists, a low level on RD enables a register OR1 or

OR2 read operation, through the bidirectional bus.

In addition, the rising edge of RD latches C/D and

the match condition pins in order to direct the inter-

nal flow of operations. Because of internal clock

resynchronization, one single additional require-

ment is recommended in order to produce a simul-

taneousinstruction flow in a multichip configuration:

the RD rising edge has to be 20 to 20 + tWL(CK) nsec

late relative to clock falling edge.

DR

Data ready. Normally high, DR output pin goes low

to tell the microprocessor that :

a) the instruction code was found to be invalid ;

b) executing instruction 5 an active output channel

was found in the whole matrix array, that is a CM

word not all ”ones” was found in a configuration of

devices sharing the same CS pins ;

c) executing instruction 6 ”0 channel extraction” took

place and OR2 was loaded with total number of

messages inserted on 0 time slot.

DR is active low about two clock cycles in case b

and c ; in case a it is left low until a valid instruction

code is supplied.

RESET

RESET control pin is normally used at the very be-

ginning to initialize the device or the network. Any

logical status is reset andCM is set to all ”ones” after

RESET going low.

The internal initialization routine takes one time

frame whatever the RESET width on low level (mini-

mum one cycle roughly), but it is repeatedan integer

number of time frames as long as RESET is found

low during 0 time slot.

Initialization pulls the interface bus immediately to a

high impedance state. After the CM has been set to

all ”ones” the PCM output channels are also set to

high impedance state.

CLOCK

Input master clock. Typical frequency is 4.096MHz.

First division gives an internal clock controlling the

input and output channels bit rate.

SYNC

Input synchronization signal is active low. Typical

frequency is 8kHz.

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