CDB4228 데이터 시트보기 (PDF) - Cirrus Logic

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CDB4228

24-Bit, 96 kHz Surround Sound Codec

Cirrus Logic 

CS4228

MAP allows successive reads or writes of consecu-

tive registers. Each byte is separated by an ac-

knowledge bit.

Control Port Bit Definitions

All registers are read/write, except the Chip Status

register which is read-only. For more detailed in-

formation, see the bit definition tables starting on

page 19.

Power-up/Reset/Power Down Mode

Upon power up, the user should hold RST = 0 until

the power supplies and clocks stabilize. In this

state, the control registers are reset to their default

settings, and the device remains in a low power

mode in which the control port is inactive. The part

may be held in a low power reset state by clearing

the DIGPDN bit in the Chip Control register. In this

state, the digital portions of the CODEC are in re-

set, but the control port is active and the desired

register settings can be loaded. Normal operation is

achieved by setting the DIGPDN bit to 1, at which

time the CODEC powers up and normal operation

begins.

The CS4228 will enter a stand-by mode if the mas-

ter clock source stops for approximately 10 µs or if

the number of MCLK cycles per LRCK period var-

ies by more than 32. Should this occur, the control

registers retain their settings.

CS

CCLK

CHIP

ADDRESS

MAP

DATA

CDIN

0010000

R/W

MSB

LSB

byte 1 byte n

MAP = Memory Address Pointer

CHIP

ADDRESS

0010000 R/W

Figure 13. Control Port Timing, SPI mode

SDA

Note 1

001000 AD0 R/W ACK D7:0 ACK D7:0

ACK

SCL

Start

Stop

Note 1: If operation is a write, this byte contains the Memory Address Pointer, MAP.

Figure 14. Control Port Timing, I2C Mode

DS307PP1

17

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