74LVU04 데이터 시트보기 (PDF) - System Logic Semiconductor
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74LVU04 Datasheet PDF : 6 Pages
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SL74LVU04
V min max min max min max
IIH
High-Level
VI= VÑÑ
Input Leakage
Current
5.5 -
0.1
-
1.0
-
1.0
ICC
Quiescent
VI=0 Â or VÑÑ 5.5
-
4.0
-
20
-
40
ìA
Supply Current
(per Package)
IO = 0 ìA
ICC1
Additional
Quiescent
VI = VÑÑ - 0.6V 2.7
-
0.2
-
0.5
-
0.85 mA
3.6 -
0.2
-
0.5
-
0.85
Supply Current
-
on input
AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tLH =tHL = 2.5 ns, RL=1 kÙ)
Symbol
Guaranteed Limit
Parameter
Test
VCC
Conditions V
25°C
Min max
-40°C ÷ 85°C -40°C ÷ 125°C
min max min max
Unit
tPHL (tPLH) Propagation
VI=0 V or 1.2
-
70
-
80
-
100
ns
Delay, Input A V1
2.0
-
22
-
26
-
31
to Output Y
tLH = tHL
2.7
-
16
-
19
-
23
(Figure 1 )
=2.5 ns
3.0
-
13
-
15
-
18
ÑL = 50 pF 4.5
-
11
-
13
-
16
RL = 1 kÙ
CI
Input
Capacitance
5.5
-
7.0
-
-
-
-
pF
CPD
Power Dissipation Capacitance (Per Inverter)
ÒÀ=25°Ñ, VI=0V or VCC
pF
36
Used to determine the no-load dynamic power consumption:
PD = CPDVCC2fI+ (CLVCC2fo), fI - input frequency, fo - output frequency (MHz)
(CLVCC2fo) – sum of the outputs
SLS System Logic
4
Semiconductor
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