SL74HC174N 데이터 시트보기 (PDF) - System Logic Semiconductor
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SL74HC174N
System Logic Semiconductor
SL74HC174N Datasheet PDF : 5 Pages
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SL74HC174
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
tPLH, tPHL Maximum Propagation Delay, Clock to Q (Figures
1 and 4)
tPHL Maximum Propagation Delay , Reset to Q
(Figures 2 and 4)
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 4)
CIN
Maximum Input Capacitance
VCC
Guaranteed Limit
V 25 °C to ≤85°C ≤125°C Unit
-55°C
2.0 6.0
4.8
4.0 MHz
4.5 30
24
20
6.0 35
28
24
2.0 110
140
165
ns
4.5 22
28
33
6.0 19
24
28
2.0 110
140
160
ns
4.5 21
28
32
6.0 19
24
27
2.0 75
95
110
ns
4.5 15
19
22
6.0 13
16
19
-
10
10
10
pF
Power Dissipation Capacitance (Per Enabled
Output)
CPD Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC
Typical @25°C,VCC=5.0 V
62
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
VCC
Symbol
Parameter
V
tSU
Minimum Setup Time, Data to 2.0
Clock (Figure 3)
4.5
6.0
th
Minimum Hold Time, Clock to 2.0
Data (Figure 3)
4.5
6.0
trec
Minimum Recovery Time,
2.0
Reset Inactive to Clock (Figure 4.5
2)
6.0
tw
Minimum Pulse Width, Clock
2.0
(Figure 1)
4.5
6.0
tw
Minimum Pulse Width, Reset
2.0
(Figure 2)
4.5
6.0
tr, tf Maximum Input Rise and Fall
2.0
Times (Figure 1)
4.5
6.0
25 °C to
-55°C
50
10
9
5
5
5
5
5
5
75
15
13
75
15
13
1000
500
400
Guaranteed Limit
≤85°C
65
13
11
5
5
5
5
5
5
95
19
16
95
19
16
1000
500
400
≤125°C
75
15
13
5
5
5
5
5
5
110
22
19
110
22
19
1000
500
400
pF
Unit
ns
ns
ns
ns
ns
ns
SLS
System Logic
Semiconductor
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