GS1515-CTM 데이터 시트보기 (PDF) - Gennum -> Semtech
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GS1515-CTM Datasheet PDF : 17 Pages
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During pathological signals, the amount of jitter that the
phase detector will add can be calculated. By choosing the
proper loop bandwidth, the amount of phase detector
induced jitter can also be limited. Typically, for a 1.41MHz
loop bandwidth at 0.2UI input jitter modulation, the phase
detector induced jitter is about 0.015UIp-p. This is not very
significant, even for the pathological signals.
CHARGE PUMP
The charge pump in a slew PLL is different from the charge
pump in a linear PLL. There are two main functions of the
charge pump. One function is to hold the frequency
information of the input data. This information is held by
CCP1, which is connected between LFS and LFS. The other
capacitor, CCP2 between LFS and LFA_GND is used to
remove common mode noise. Both CCP1, CCP2 should be
the same value. The second function of the charge pump is
to provide a binary control voltage to the VCO depending
upon the phase detector output. The output pin, LFA
controls the VCO. Internally there is a 500Ω pull-up resistor,
which is driven with a 100µA current called ΙP. Another
analog current ΙF, with 5mA maximum drive proportional to
the voltage across the CCP1 is applied at the same node.
The voltage at the LFA node is VLFA_VCC - 500(ΙP+ΙF) at any
time.
Because of the integrator, ΙF changes very slowly, whereas
ΙP could change at the positive edge of the data transition
as often as a clock period. In the locked position, the
average voltage at the LFA (VLFA_VCC – 500(ΙP/2+ΙF)) is such
that VCO generates frequency ƒ, equal to the data rate
clock frequency. Since ΙP is changing all the time between
0A and 100µA, there will be two levels generated at the LFA
output.
VCO
The GO1515 is an external hybrid VCO, which has a centre
frequency of 1.485GHz and is also guaranteed to provide
1.485/1.001GHz within the control voltage (3.1V – 4.65V) of
the GS1515 over process, power supply and temperature.
The GO1515 is a very clean frequency source and because
of the internal high Q resonator, it is an order of magnitude
more immune to external noise as compared to on-chip
VCOs.
The VCO gain, Kƒ, is nominally 16MHz/V. The control
voltage around the average LFA voltage will be 500 x ΙP/2.
This will produce two frequencies off from the centre by
ƒ=Kƒ x 500 x ΙP/2.
LOOP BANDWIDTH OPTIMIZATION
Since the feed back loop has only digital circuits, the small
signal analysis does not apply to the system. The effective
loop bandwidth scales with the amount of input jitter
modulation index. The following table summarizes the
relationship between input jitter modulation index and
bandwidth when RCP1 and CCP3 are not used. See the
Typical Application Circuit artwork for the location of RCP1
and CCP3.
INPUT JITTER
MODULATION
INDEX
0.05
0.10
0.20
0.50
BANDWIDTH
5.657MHz
2.828MHz
1.414MHz
565.7kHz
BW JITTER
FACTOR
(jitter modulation x
BW)
282.9kHzUI
282.9kHzUI
282.9kHzUI
282.9kHzUI
The product of the input jitter modulation (IJM) and the
bandwidth (BW) is a constant. In this case, it is 282.9kHzUI.
The loop bandwidth automatically reduces with increasing
input jitter, which helps in cleaning up the signal as much
as possible.
Using a series combination of RCP1 and CCP3 in parallel to
an on-chip resistor (as shown in the Typical Application
Circuit) can reduce the loop bandwidth of the GS1515. The
parallel combination of the resistor is directly proportional to
the bandwidth factor. For example, the on-chip 500Ω
resistor yields 282.9kHzUI. If a 50Ω resistor is connected in
parallel, the effective resistance will be (50 || 500) 45.45Ω.
This resistance yields a bandwidth factor of
[282.9 X (45.45/500)] = 25.72kHzUI. The capacitance CCP3
in series with the RCP1 should be chosen such that the RC
factor is 50µF. For example, RCP1=50Ω would require
CCP3=1µF.
The synchronous lock time increases with reduced
bandwidth. Nominal synchronous lock time is equal to
[ 0.25 × 2 /Bandwidth factor]. That is, the default
bandwidth factor (282.9kHzUI) would yield 1.25µs. For
25.72kHzUI, the synchronous lock time is
0.3535/25.72k=13.75µs. Since the CCP1, CCP2 and CCP3 are
also charged, it is measured to be about 11µs which is
slightly less than the calculated value of 13.75µs.
The Kƒ of the VCO (GO1515) is specified with a minimum of
11MHz/V and maximum of 21MHz/V which is about ±32%
variation. The 500 x ΙP/2 will vary about ±10%. The resulting
bandwidth factor would approximately vary by ±45% when
no RCP1 and CCP3 are used. ΙP by itself may vary by 30% so
the variability for lower bandwidths will increase by an
additional ±30%.
The CCP1 and CCP2 capacitors should be changed with
reduced bandwidths. Smaller CCP1 and CCP2 capacitors
would result in jitter peaking, lower stability, less probability
of locking but at the same time lowering the asynchronous
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