Preliminary W6662CF
7.6 Timing Characteristics, continued
PARAMETER
SYM.
Data Output
Digital Output Delay
tDOD
Output Enable to Data Delay
tOED
Output Disable to Data tri-state tODZ
Digital Output Latency
Serial Interface
Maximum SCLK Frequency
fSCLK
SEN to SCLK set-up time
tSES
SCLK to SEN hold time
tSEH
SDI input to SCLK set-up time tSIS
SCLK to SDI input hold time
tSIH
SCLK falling to SDO output
tSOE
enable time
SDO output delay time
tSOD
SEN to SDO output tri-state
tSOZ
delay time
MIN.
10
10
15
10
TYP.
MAX.
40
20
20
3
24
10
15
10
UNITS
nS
nS
nS
ADCCLKcycles
MHz
nS
nS
nS
nS
nS
nS
nS
NOTES
Analog
input
CDSCK1
CDSCK2
ADCCLK
DOUT
tACD
tCLP
(PIXn)
tACD
tC2S
tS2C
(PIXn+1)
tCVR
tSPD
(PIXn+2)
(PIXn+3)
(PIXn+4)
tADCL
tS2AD
(PIXn-5)
tADCH
tDOD
(PIXn-4)
Latency
(PIXn-3)
0
(PIXn-2)
1
Fig. 7-1 Timing of CDS Mode.
(PIXn-1)
2
(PIXn)
3
- 13 -
Publication Release Date: December 1998
Revision A1