Philips Semiconductors
IEC 958 audio DAC
Preliminary specification
UDA1350AH
The UDA1350AH can operate in various operating modes:
• IEC 958 input to the DAC including on-chip signal
processing
• IEC 958 input via the digital data output interface to the
external Digital Signal Processor (DSP)
• IEC 958 input to the DAC and a DSP
• IEC 958 input via a DSP to the DAC including on-chip
signal processing
• External source data input to the DAC including on-chip
signal processing.
The IEC 958 input audio data including the accompanying
pre-emphasis information is available on the output data
interface.
A lock indication signal is available on pin LOCK indicating
that the IEC 958 decoder is locked. By default the DAC
output and the data output interface are muted when the
decoder is out-of-lock. However, this setting can be
overruled in the L3 control mode.
4 QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Supplies
VDDA
VDDD
IDDA(DAC)
IDDA(PLL)
IDDD
IDDD(C)
P
analog supply voltage
digital supply voltage
analog supply current of DAC
analog supply current of PLL
digital supply current
digital supply current of core
power consumption
2.7 3.0 3.6 V
2.7 3.0 3.6 V
power-on
−
8.0 −
mA
power-down
−
750 −
µA
−
0.7 −
mA
−
2.0 −
mA
−
16.0 −
mA
DAC in playback mode −
80
−
mW
DAC in Power-down mode −
58
−
mW
General
trst
Tamb
reset active time
ambient temperature
Digital-to-analog converter
−
250 −
µs
−40 −
+85 °C
Vo(rms)
(THD + N)/S
S/N
αcs
∆Vo
output voltage (RMS value)
note 1
−
total harmonic distortion-plus-noise to fi = 1.0 kHz tone
signal ratio
at 0 dB
−
at −40 dB; A-weighted −
signal-to-noise ratio
fi = 1.0 kHz tone;
95
code = 0; A-weighted
channel separation
fi = 1.0 kHz tone
−
unbalance of output voltages
fi = 1.0 kHz tone
−
900 −
mV
−90 −85 dB
−60 −55 dB
100 −
dB
96
−
dB
0.1 0.4 dB
Note
1. The DAC output voltage is proportional to the DAC power supply voltage.
1999 Dec 16
4