GTLP6C816
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Functional Description
The GTLP6C816 is a clock driver that provides TTL to GTLP clock
translation, and GTLP-to-TTL clock translation. The TTL-to-GTLP
direction is a 1:2 clock driver path with a single Enable pin (OEB).
For the GTLP -to-TTL direction, the clock receiver path is a 1:6 buffer
with a single Enable control (OEA). Data polarity is inverting for
both directions.
Pin Descriptions
Pin Names
Description
TTLIN, GTLPIN Clock Inputs (TTL and GTLP respectively)
OEB
Output Enable (Active LOW) GTLP Port (TTL Levels)
OEA
Output Enable (Active LOW) TTL Port (TTL Levels)
VCCT, GNDT
TTL Output Supplies (5V)
VCC
Internal Circuitry VCC (5V)
GNDG
OBn GTLP Output Grounds
VREF
Voltage Reference Input
OA0 - OA5
TTL Buffered Clock Outputs
OB0 - OB5
GTLP Buffered Clock Outputs
Truth Table
Inputs
TTLIN
OEB
H
L
L
L
X
H
GTLPIN OEA
H
L
L
L
X
H
Outputs
OBn
L
H
High Z
OAn
L
H
High Z
2
PS8426A 03/15/00