GTLP6C816 데이터 시트보기 (PDF) - Pericom Semiconductor
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GTLP6C816 Datasheet PDF : 6 Pages
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GTLP-to-TTL 1:6 Clock Driver
Features
Bidirectional interface between GTLP and TTL
logic levels
Designed with Edge Rate Control Circuit to
reduce output noise on the GTLP port
Power up/down high impedance for live insertion
1:6 fanout clock driver for TTL port
Lower Drive (12mA) on TTL Port to reduce noise
1:2 fanout clock driver for GTLP port
TTL compatible driver and control inputs
Flow -through architecture optimizes PCB layout
Open drain on GTLP to support wired-or connection
Operating Temperature: 40°C to +85°C
Package:
24-Pin 173 mil wide plastic TSSOP (L24)
Product Description
Pericom Semiconductors GTLP series of logic circuits are produced
using the Companys advanced 0.5 micron CMOS technology,
achieving industry leading performance.
The GTLP6C816 is a clock driver that provides TTL to GTLP signal
level translation (and vice versa). The device provides a high-speed
interface between cards operating at TTL logic levels and a backplane
operating at GTLP logic levels. High-speed backplane operation is
a direct result of GTLPs reduced output swing (<1V), reduced input
threshold levels, and output edge-rate control which minimizes bus
settling times.
Pericoms GTLP has internal edge-rate control. Its function is similar
to BTL or GTL but with different output levels and receiver threshold.
GTLP output low voltage is typically less than 0.5V, the output level
HIGH is 1.5V and the receiver threshold is 1.0V.
Logic Block Diagram
TTLIN
OEA
OA0
OA1
PoTrTtLs
OA5
OEB
OB0
OB1
GPoTrLtPs
GTLPIN
PinConfiguration
TTLIN
OA0
GNDT
OA1
VCCT
OA2
GNDT
OA3
VCCT
OA4
GNDT
OA5
1
24
2
23
3
22
4
21
5
20
6 24-Pin 19
7
L 18
8
17
9
16
10
15
11
14
12
13
GNDT
OEB
OB0
GNDG
VREF
GNDG
VCC
OB1
GNDG
GTLPIN
OEA
GNDT
1
PS8426A 03/15/00
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