RMWP23001 데이터 시트보기 (PDF) - Fairchild Semiconductor
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RMWP23001 Datasheet PDF : 9 Pages
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DRAIN SUPPLY
Vd = +4V
1µF
L
10,000pF
RF IN
L
100pF
L
MMIC CHIP
L
100pF
L
L
100pF
L
L
100pF
L
RF OUT
GROUND
(Back of Chip)
L
100pF
L = BOND WIRE INDUCTANCE
GATE SUPPLY
Vg
Figure 3. Recommended Application Schematic Circuit Diagram
10,000pF
5 MIL THICK
ALUMINA
50Ω
RF INPUT
100pF
100pF
100pF
Vdd (POSITIVE)
1µF
DIE-ATTACH
80Au/20Sn
100pF
5 MIL THICK
ALUMINA
50Ω
RF OUTPUT
100pF
L < 0.015"
(4 Places)
2 MIL GAP
Vg (NEGATIVE)
Note:
Use 0.003" by 0.0005" Gold Ribbon for bonding. RF input and output bonds should be less than 0.015" long with stress relief.
Figure 4. Recommended Assembly Diagram
©2004 Fairchild Semiconductor Corporation
RMWP23001 Rev. C
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