PI6C9911J 데이터 시트보기 (PDF) - Pericom Semiconductor
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PI6C9911J Datasheet PDF : 9 Pages
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PI6C9911 & PI6C9911E
5V High Speed Programmable Skew
Clock Buffers - SuperClock®
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Test Mode
Maximum Ratings
The TEST input is a three-level input. In normal system operation,
this pin is connected to ground, allowing the PI6C9911 to
operate as explained briefly above (for testing purposes, any of the
three-level inputs can have a removable jumper to ground, or be
tied LOW through a 100 ohm resistor. This will allow an external
tester to change the state of these pins).
If the TEST input is forced to its MID or HIGH state, the device will
operate with its internal phase locked loop disconnected, and in-
put levels supplied to REF will directly control all outputs.
Relative output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW). All outputs
will function based only on the connection of their own function
select inputs (xF0 and xF1) and the waveform characteristics of the
REF input.
(Above which the useful life may be impaired)
Storage Temperature ............................................ 65ºC to +150ºC
Ambient Temperature
with Power Applied ..............................................55ºC to +125ºC
Supply Voltage to Ground Potential ....................... 0.5V to +7.0V
DC Input Voltage .................................................... 0.5V to +7.0V
Output Current into Outputs (LOW) ................................... 64mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ................................. >2001V
Latch-Up Current ............................................................ >200mA
Operating Range
Range
Ambient Temperature
VCC
Commercial
Industrial
0ºC to +70ºC
40ºC to +85ºC
5V ±10%
Notes for Tables on Pages 3 through 7:
1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connections to GND, and MID indicates an open
connection. Internal termination circuitry holds an unconnected input to VCC/2.
2. The level to be set on FS is determined by the normal operating frequency (fNOM) of the VCO and the Time Unit Generator (see
Logic Block Diagram). Nominal frequency (fNOM) always appears at 1Q0 and the other outputs when they are operated in their
undivided modes (see Table 2). The frequency appearing at the REF and FB inputs will be fNOM when the output connected to FB is
undivided.The frequency of REF and FB inputs will be fNOM/2 or fNOM /4 when the part is configured for a frequency multiplication
by using a divided output as the FB input.
3. When the FS pin is selected HIGH, the REF input must not transition upon power-up untill VCC has reached 4.3V.
4. FB connected to an output selected for zero skew (ie., xF1 = xF0 = MID).
6. These inputs are normally wired to VCC, GND, or left unconnected (actual threshhold voltages vary as a percentage of VCC). Internal
termination resistors hols unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may
glitch and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
10. Test measurement levels are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2ns or less and output
loading as shown in the AC Test Loads and Waveforms unless specified.
11. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
12. Skew is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has
been selected when all are loaded with 30pF and terminated with 50Ω to 2.06V.
13. tSKEWPR is defined as the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
14. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
15. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided
(3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).
16. tDEV is the output-to-output skew between any 2 devices operating under the same conditions (VCC ambient temperature, air flow, etc.).
17. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4
specifications.
18. Specified with outputs loaded with 30pF. Devices are terminated through 50Ω to 2.06V.
19. tPWH is measured at 2.0V. tPWL is measured at 0.8V
20. tORISE and tOFALL measured between 0.8V and 2.0V.
21. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within
normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until t PD is within
specified limits.
4
PS8451B 03/28/01
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