MC74HCT74ADR2G(2014) 데이터 시트보기 (PDF) - ON Semiconductor

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MC74HCT74ADR2G
(Rev.:2014)

Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs

ON Semiconductor 

MC74HCT74A

Dual D Flip-Flop with Set

and Reset with LSTTL

Compatible Inputs

High−Performance Silicon−Gate CMOS

The MC74HCT74A is identical in pinout to the LS74. This device

may be used as a level converter for interfacing TTL or NMOS outputs

to High Speed CMOS inputs.

This device consists of two D flip−flops with individual Set, Reset,

and Clock inputs. Information at a D−input is transferred to the

corresponding Q output on the next positive going edge of the clock

input. Both Q and Q outputs are available from each flip−flop. The Set

and Reset inputs are asynchronous.

Features

• Output Drive Capability: 10 LSTTL Loads

• TTL NMOS Compatible Input Levels

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 4.5 to 5.5 V

• Low Input Current: 1.0 mA

• In Compliance With the JEDEC Standard No. 7.0 A Requirements

• Chip Complexity: 136 FETs or 34 Equivalent Gates

• These Devices are Pb−Free, Halogen Free and are RoHS Compliant

LOGIC DIAGRAM

RESET 1 1

DATA 1 2

3

CLOCK 1

SET 1 4

13

RESET 2

DATA 2 12

11

CLOCK 2

10

SET 2

5

Q1

6

Q1

PIN 14 = VCC

PIN 7 = GND

9

Q2

8

Q2

Design Criteria

Value

Internal Gate Count†

34

Internal Gate Propagation Delay

1.5

Internal Gate Power Dissipation

5.0

Speed Power Product

.0075

†Equivalent to a two−input NAND gate.

Units

ea.

ns

mW

pJ

© Semiconductor Components Industries, LLC, 2014

1

September, 2014 − Rev. 12

http://onsemi.com

SOIC−14 NB

D SUFFIX

CASE 751A

PIN ASSIGNMENT

RESET 1 1

DATA 1 2

CLOCK 1 3

SET 1 4

Q1 5

Q1 6

GND 7

14 VCC

13 RESET 2

12 DATA 2

11 CLOCK 2

10 SET 2

9 Q2

8 Q2

MARKING DIAGRAM

14

HCT74AG

AWLYWW

1

A

WL

Y, YY

WW

G

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

FUNCTION TABLE

Inputs

Set Reset Clock Data

LH

HL

LL

HH

HH

HH

HH

HH

XX

XX

XX

H

L

LX

HX

X

Outputs

QQ

HL

LH

H* H*

HL

LH

No Change

No Change

No Change

*Both outputs will remain high as long as Set and

Reset are low, but the output states are unpredict-

able if Set and Reset go high simultaneously.

ORDERING INFORMATION

See detailed ordering and shipping information on page 3 of

this data sheet.

Publication Order Number:

MC74HCT74A/D

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