MC74HC540 데이터 시트보기 (PDF) - ON Semiconductor
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MC74HC540 Datasheet PDF : 8 Pages
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MC74HC540A
tr
INPUT A
tPHL
OUTPUT Y
90%
50%
10%
90%
50%
10%
tf
VCC
GND
tPLH
tTHL
tTLH
Figure 3. Switching Waveform
OE1 or OE2
tPZL
OUTPUT Y
tPZH
OUTPUT Y
50%
tPLZ
50%
tPHZ
50%
50%
10%
90%
Figure 4. Switching Waveform
VCC
GND
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ and tPZH.
*Includes all probe and jig capacitance
Figure 5. Test Circuit
INPUT A
To 7 Other Inverters
One of Eight
Inverters
*Includes all probe and jig capacitance
Figure 6. Test Circuit
VCC
OUTPUT Y
OE1
OE2
Figure 7. Logic Detail
PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, 9)
Data input pins. Data on these pins appear in inverted form
on the corresponding Y outputs, when the outputs are
enabled.
CONTROLS
OE1, OE2 (PINS 1, 19)
Output enables (active−low). When a low voltage is
applied to both of these pins, the outputs are enabled and the
device functions as an inverter. When a high voltage is
applied to either input, the outputs assume the high
impedance state.
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11)
Device outputs. Depending upon the state of the output
enable pins, these outputs are either inverting outputs or
high−impedance outputs.
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