MB90440G(2008) 데이터 시트보기 (PDF) - Fujitsu
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MB90440G Datasheet PDF : 64 Pages
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MB90440G Series
6. Pull-up/down resistors
The MB90440G Series does not support internal pull-up/down resistors (except pull-up resistors of port 0 to
port 3) . Use external components needed.
7. Crystal Oscillator Circuit
Noises around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via the
shortest distances from X0 and X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make
sure, to the utmost effort, that lines of oscillation circuits do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
8. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D and D/A converters power supply (AVCC, AVRH, AVRL) and analog inputs (AN0
to AN7) after turning on the digital power supply (VCC) .
Turn off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that AVRH does not exceed AVCC (turning on/off the analog and digital power supplies simultaneously is accept-
able) .
9. Connection of Unused Pins of A/D Converter
Connect unused pins of A/D and D/A converters to AVCC = VCC, AVSS = AVRH = VSS.
10. N.C. Pin
The N.C. (internally connected) pin must be opened for use.
11. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
µs or more (0.2 V to 2.7 V) .
12. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers,
please turn on the power again.
13. Using REALOS
The use of (EI2OS) is not possible with the REALOS real time operation system.
14. Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected in the microcontroller, it may attempt to continue the operation using the free-
running frequency of the automatic oscillating circuit in the PLL circuitly even if the oscillator is out of place or
the clock input is stopped. Performance of this operation, however, cannot be guaranteed.
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DS07-13716-3E
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