M65665CFP 데이터 시트보기 (PDF) - Renesas Electronics
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M65665CFP Datasheet PDF : 18 Pages
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M65665CFP/SP
Basic Application Example
When using any or all of the information contained in this diagrams, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products.
Dig.
Digital +3.3V power supply
Digital GND
Ana. Analog +3.3V power supply
Analog GND
22 pin input level
Sub C(Y/C) input 0.01u 22
pedestal
0.7Vpp(typ)
23
Sub CVBS and Y(Y/C) input 0.1u 24
white peak
24 pin input level
0.47u 3.3 K
25
0.66V(max)
1.0Vpp
(max)
0.033u
26
3.3 M
pedestal
sync tip
0.22u
18 p
27
0
X1
28
X1 : SIWARD 1-781-377-21(14.31818MHz) 29
30
31
32 pin /33 pin input level Main HD input
32
3.3V-5.0V
0V Main VD input
33
36 pin output level
34
pedestal
0.7Vpp (typ) OSD B input 0.1u 35
PIP V(B) output 0.01u 36
39 pin output level
0.01u 37
pedestal
0.7Vpp (typ) OSD G input 0.1u 38
PIP U(G) output
39
0.01u
42 pin output level
white peak
OSD R input
40
0.1u 41
back ground
0.7V (typ) PIP Y(R) output 0.01u 42
pedestal
20 pin input level
0.66V
(max)
1.0Vpp
(max)
white peak
21 0.01u
pedestal
sync tip
20 0.1u Sub Y(Y/U/V) input
19 0.01u
18 pin input level
0.7Vpp (typ)
18 0.1u Sub U input
pedestal
17 0.1u Sub V input 17 pin input level
16
0.7Vpp (typ)
pedestal
15
14
10u
13
10K
12
11
10
15 pin input when CSYNC
of sub picture is fed from
9
external.
3.3V
8
0V
7
2 pin input level
6
3.3V
0V
5
4
I2C BUS Clock input
3
I2C BUS DATA input /output
2
OSD selection input
1
PIP SW output 1 pin output level
3.3V
0V
Rev.2.00, Sep.04.2003, page 7 of 17
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