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7641

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Mitsumi 

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MITSUBISHI MICROCOMPUTERS

7641 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

NOTES ON PROGRAMMING

Processor Status Register

•The contents of the processor status register (PS) after a reset

are undefined, except for the interrupt disable flag (I) which is “1”.

After a reset, initialize flags which affect program execution. In

particular, it is essential to initialize the index X mode (T) and the

decimal mode (D) flags because of their effect on calculations.

•To reference the contents of the processor status register (PS),

execute the PHP instruction once then read the contents of

(S+1). If necessary, execute the PLP instruction to return the PS

to its original status.

A NOP instruction must be executed after every PLP instruction.

•A SEI instruction must be executed before every PLP instruction.

A NOP instruction must be executed before every CLI instruction.

BRK Instruction

It can be detected that the BRK instruction interrupt event or the

least priority interrupt event by referring the stored B flag state.

Refer to the stored B flag state in the interrupt routine.

Decimal Calculations

When decimal mode is selected, the values of the V flags are in-

valid.

The carry flag (C) is set to “1” if a carry is generated as a result of

the calculation, or is cleared to “0” if a borrow is generated. To de-

termine whether a calculation has generated a carry, the C flag

must be initialized to “0” before each calculation. To check for a

borrow, the C flag must be initialized to “1” before each calcula-

tion.

Multiplication and Division Instructions

•The index X mode (T) and the decimal mode (D) flags do not af-

fect the MUL and DIV instruction.

Instruction Execution Time

The instruction execution time is obtained by multiplying the fre-

quency of the internal clock φ by the number of cycles needed to

execute an instruction.

The number of cycles required to execute an instruction is shown

in the list of machine instructions.

Timers

•If a value n (between 0 and 255) is written to a timer latch, the

frequency division ratio is 1/(n+1).

•P51/XCOUT/TOUT pin cannot function as an I/O port when XCIN -

XCOUT is oscillating. When XCIN - XCOUT oscillation is not used or

XCOUT oscillation drive is disabled, this pin can function as the

TOUT output pin of the timer 1 or 2.

When using the TOUT output function and f(XCIN) divided by 2 is

used as the timer 1 count source (bit 2 of T123M = “1”), disable

XCOUT oscillation drive (bit 5 of CCR = “1”).

Ports

•When the data register (port latch) of an I/O port is modified with

the bit managing instruction (SEB, CLB instructions) the value of

the unspecified bit may be changed.

•In standby state (the stop mode by executing the STP instruction,

and the wait mode by executing the WIT instruction) for low-

power dissipation, do not make input levels of an I/O port

“undefined”, especially for I/O ports of the P-channel and the N-

channel open-drain.

Pull-up (connect the port to Vcc) or pull-down (connect the port to

Vss) these ports through a resistor.

When determining a resistance value, note the following points:

(1) External circuit

(2) Variation of output levels during the ordinary operation

When using built-in pull-up or pull-down resistor, note on varied

current values.

(1) When setting as an input port : Fix its input level

(2) When setting as an output port : Prevent current from flowing

out to external

Serial I/O

Do not write to the serial I/O shift register during a transfer when in

SPI compatible mode.

UART

•The all error flags PER, FER, OER and SER are cleared to “0”

when the UARTx status register is read, at the hardware reset or

initialization by setting the Transmit Initialization Bit. These flags

are also cleared to “0” by execution of bit test instructions such as

BBC and BCS.

•The transmission interrupt request bit is set and the interrupt re-

quest is generated by setting the transmit enable bit to “1” even

when selecting timing that either of the following flags is set to “1”

as timing where the transmission interrupt is generated:

(1) Transmit buffer empty flag is set to “1”

(2) Transmit complete flag is set to “1”.

Therefore, when the transmit interrupt is used, set the transmit in-

terrupt enable bit to transmit enabled as the following sequence:

(1) Transmit enable bit is set to “1”

(2) Transmit interrupt request bit is set to “0”

(3) Transmit interrupt enable bit is set to “1”.

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