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7641

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Mitsumi 

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MITSUBISHI MICROCOMPUTERS

7641 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Functions To Inhibit Rewriting Flash Memory

Version

To prevent the contents of internal flash memory from being read

out or rewritten easily, this MCU incorporates a ROM code protect

function for use in parallel I/O mode and an ID code check func-

tion for use in standard serial I/O mode.

qROM Code Protect Function

The ROM code protect function is the function to inhibit reading

out or modifying the contents of internal flash memory by using

the ROM code protect control register (address FFC916) in paral-

lel I/O mode. Figure 94 shows the ROM code protect control

register (address FFC916). (This address exists in the User ROM

area.)

If one or both of the pair of ROM Code Protect Bits is set to “0”,

the ROM code protect is turned on, so that the contents of internal

flash memory are protected against readout and modification. The

ROM code protect is implemented in two levels. If level 2 is se-

lected, the flash memory is protected even against readout by a

shipment inspection LSI tester, etc. When an attempt is made to

select both level 1 and level 2, level 2 is selected by default.

If both of the two ROM Code Protect Reset Bits are set to “00”, the

ROM code protect is turned off, so that the contents of internal

flash memory can be read out or modified. Once the ROM code

protect is turned on, the contents of the ROM Code Protect Reset

Bits cannot be modified in parallel I/O mode. Use the serial I/O or

CPU rewrite mode to rewrite the contents of the ROM Code Pro-

tect Reset Bits.

b7

b0

1 1 ROM code protect control register (address FFC916) (Note 1)

ROMCP

Reserved bits (“1” at read/write)

ROM code protect level 2 set bits (ROMCP2) (Notes 2, 3)

b3b2

0 0: Protect enabled

0 1: Protect enabled

1 0: Protect enabled

1 1: Protect disabled

ROM code protect reset bits (Note 4)

b5b4

0 0: Protect removed

0 1: Protect set bits effective

1 0: Protect set bits effective

1 1: Protect set bits effective

ROM code protect level 1 set bits (ROMCP1) (Note 2)

b7b6

0 0: Protect enabled

0 1: Protect enabled

1 0: Protect enabled

1 1: Protect disabled

Notes 1: This area is on the ROM in the mask ROM version.

2: When ROM code protect is turned on, the internal flash memory is protected

against readout or modification in parallel I/O mode.

3: When ROM code protect level 2 is turned on, ROM code readout by a shipment

inspection LSI tester, etc. also is inhibited.

4: The ROM code protect reset bits can be used to turn off ROM code protect level 1

and ROM code protect level 2. However, since these bits cannot be modified in

parallel I/O mode, they need to be rewritten in standard serial I/O mode or CPU

rewrite mode.

Fig. 94 Structure of ROM code protect control register

111

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