LY6212816 데이터 시트보기 (PDF) - Lyontek Inc.

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LY6212816

128K X 16 BIT LOW POWER CMOS SRAM

Lyontek Inc. 

®

Rev. 1.3

LY6212816

128K X 16 BIT LOW POWER CMOS SRAM

WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6)

Address

CE#

LB#,UB#

tWC

tAW

tAS

tCW

tBW

WE#

Dout

tWP

tWHZ

(4)

Din

tWR

High-Z

tDW

tDH

Data Valid

Notes :

1.WE#,CE#, LB#, UB# must be high during all address transitions.

2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.

3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be

placed on the bus.

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance

state.

6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

Lyontek Inc. reserves the rights to change the specifications and products without notice.

5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.

TEL: 886-3-6668838

FAX: 886-3-6668836

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