LY621024UL 데이터 시트보기 (PDF) - Lyontek Inc.
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LY621024UL Datasheet PDF : 16 Pages
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®
Rev. 1.5
LY621024
128K X 8 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER
VCC for Data Retention
Data Retention Current
Chip Disable to Data
Retention Time
Recovery Time
tRC* = Read Cycle Time
SYMBOL
TEST CONDITION
VDR CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V
LL
LLE/LLI
IDR
VCC = 1.5V
CE# ≧ VCC - 0.2V
or CE2 ≦ 0.2V
Other pins at 0.2V
or
VCC-0.2V
SL
SLE
SLI
25℃
40℃
SL
SLE/SLI
tCDR
See Data Retention
Waveforms (below)
tR
MIN.
1.5
-
-
-
-
-
-
0
tRC*
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
TYP.
-
0.5
0.5
0.4
0.5
0.4
0.4
-
-
MAX.
5.5
12
30
2
UNIT
V
µA
µA
µA
2
µA
5
µA
8
µA
-
ns
-
ns
Vcc
CE#
Vcc(min.)
tCDR
VIH
VDR ≧ 1.5V
CE# ≧ Vcc-0.2V
Vcc(min.)
tR
VIH
Low Vcc Data Retention Waveform (2) (CE2 controlled)
Vcc
CE2
Vcc(min.)
tCDR
VIL
VDR ≧ 1.5V
CE2 ≦ 0.2V
Vcc(min.)
tR
VIL
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
8
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